ODELAYE3 Ports

UltraScale Architecture SelectIO Resources User Guide (UG571)

Document ID
UG571
Release Date
2022-08-31
Revision
1.14 English

Table: ODELAYE3 Ports lists the ODELAYE3 ports.

Table 2-15:      ODELAYE3 Ports

Port

I/O

Description

CASC_RETURN

Input

The CASC_RETURN pin is the output cascade delay returning from slave IDELAYE3/ODELAYE3. The CASC_RETURN of the ODELAYE3 is connected to the slave IDELAYE3 DATAOUT port.

CASC_IN

Input

The CASC_IN pin is used when the ODELAYE3 is used in a cascade chain as a slave input cascade delay from IDELAYE3 CASC_OUT.

CASC_OUT

Output

The CASC_OUT pin is used when cascading from an ODELAYE3 to an IDELAYE3. The CASC_OUT port of the ODELAYE3 is connected to the CASC_IN of the IDELAYE3 in cascade.

CE

Input

Clock enable for the delay register clock.

Note:   Delays might take up to three clock cycles (CLK) to be applied. During this time, input data should not change to ensure output data does not glitch.

CLK

Input

All control inputs to the ODELAYE3 primitive (LOAD, CE, and INC) are synchronous to the clock input (CLK). A clock must be connected to this port when ODELAYE3 is configured in VARIABLE or VAR_LOAD modes. The CLK can be locally inverted. The CLK of the ODELAYE3 must be the same CLK as the OSERDESE3 CLKDIV or the ODDRE1 C port (UltraScale devices only). For UltraScale+ devices, the C port is remapped to CLK in XPIO banks. Unused when configured in FIXED mode.

INC

Input

The increment/decrement is controlled by the enable signal (CE). This interface is only available when the ODELAYE3 is in VARIABLE or VAR_LOAD modes. As long as CE remains High, the ODELAYE3 increments or decrements by one tap every CLK cycle. The state of INC determines whether ODELAYE3 increments or decrements; INC = 1 increments, INC = 0 decrements, synchronously to the CLK. If CE is Low, the delay through ODELAYE3 does not change regardless of the state of INC. When CE transitions High, the increment/decrement operation begins on the next positive clock edge. When CE transitions Low, the increment/decrement operation ceases on the next positive clock edge.

The programmable delay taps in the ODELAYE3 primitive wraps around to the start or end of the taps. When the last tap delay is reached (tap 512), a subsequent increment function returns to tap 0. The same applies to the decrement function—a decrement from zero moves to tap 512.

LOAD

Input

Loads counter value from attribute DELAY_VALUE or bus CNTVALUEIN. When in VAR_LOAD mode, the ODELAYE3 LOAD port loads the value set by the CNTVALUEIN into registers connected to the delay line tap selection logic. The value present at CNTVALUEIN[8:0] is the new tap value. The LOAD signal is an active-High signal and is synchronous to the input CLK signal. Wait at least one clock cycle after applying a new value on the CNTVALUEIN bus before applying the LOAD signal. CE must be held Low during LOAD operation.

When in VARIABLE mode, connect LOAD to ground (GND).

Note:   Delays might take up to three clock cycles (CLK) to be applied. During this time, input data should not change to ensure output data does not glitch.

CNTVALUEIN[8:0]

Input

The CNTVALUEIN pins are used for dynamically switching the loadable tap value. The CNTVALUEIN is the number of taps required. The new value is best applied one clock cycle before applying the LOAD signal. The delay line can be changed from 1 to 8 taps at a time.

CNTVALUEOUT[8:0]

Output

The CNTVALUEOUT pins are used for reporting the current tap value and reads out the amount of taps in the current delay. When EN_VTC is High, CNTVALUEOUT is updated by the IDELAYCTRL.

ODATAIN

Input

The ODATAIN input is driven by the ODDRE1Q port or the OSERDESE3 (OQ).

DATAOUT

Output

The DATAOUT port is the output port of the ODELAYE3 and connects to the output IOB.

RST

Input

The RST pin (reset) is an asynchronous input. When the ODELAYE3 is reset, the delay is set to the value defined by the DELAY_VALUE attribute. RST must follow the Component Mode Reset Sequence when used with the IDELAYCTRL. After IDELAYCTRL.RDY goes High, ODELAY can be used for normal operation.

EN_VTC

Input

EN_VTC: Enable voltage temperature compensation.

High: Enables IDELAYCTRL to keep delay constant over VT.

Low: VT compensation is disabled.

To make delay line updates, EN_VTC is an asynchronous input but must be kept Low. EN_VTC must follow the Component Mode Reset Sequence when used with the IDELAYCTRL.