OPPOSITE_EDGE Mode

UltraScale Architecture SelectIO Resources User Guide (UG571)

Document ID
UG571
Release Date
2022-08-31
Revision
1.14 English

OPPOSITE_EDGE mode, a traditional input DDR solution, is accomplished using a single input in the ILOGIC block. The data is presented to the device logic though the output Q1 on the rising edge of the clock and the output Q2 on the falling edge of the clock. This structure is similar to the 7 series FPGA implementation. This Figure shows the timing diagram of the input DDR using the OPPOSITE_EDGE mode.

Figure 2-4:      Input DDR Timing in OPPOSITE_EDGE Mode

X-Ref Target - Figure 2-4

X16005-input-ddr-timing-in-opposite_edge-mode.jpg