The OSERDESE3 primitive is available to perform output serialization for designs migrating from previous FPGA families or for designs not requiring native mode primitives. The OSERDESE3 in UltraScale devices is a 4- or 8-bit parallel-to-serial converter with specific clocking features to facilitate the implementation of source-synchronous and other applications. If other serial-to-parallel conversion factors are required, use the ODDRE1 primitive or implement a gearbox in internal logic.
There are some differences between the OSERDESE3 and its predecessors. The following functionality is not available in the OSERDESE3:
•OCE input enable pin for the serial output of the OSERDES.
•SHIFTIN and SHIFTOUT pins can use local dedicated connections to extend the serialization capabilities of the OSERDES.
•OFB output providing a straight and direct connection between the OSERDES output and ISERDES input without using an input and/or output buffer (IOB) and pin.
•Parallel 3-state and serial TBYTE functionality.
The latency through the OSERDES depends on the DATA_WIDTH setting as shown in This Figure.
The OSERDESE3 can serialize an outgoing signal by a 2 or 4 in SDR mode, or by a 4 or 8 in DDR mode. When used with SDR clocking, the DATA_WIDTH attribute is to be set to twice the desired width and data to be transmitted should be applied to two pins at a time. See This Figure.
The full range of possibilities together with the associated attribute settings and required connections are shown in Table: OSERDESE3 Output Connections in SDR and DDR Modes .
TIP: The data applied to SerDes input D0 is the first bit to be transmitted in all cases.