OSERDESE3 Attributes

UltraScale Architecture SelectIO Resources User Guide (UG571)

Document ID
UG571
Release Date
2022-08-31
Revision
1.14 English

Table: OSERDESE3 Attributes lists the OSERDESE3 attributes.

Table 2-10:      OSERDESE3 Attributes

Attribute

Values

Default

Type

Description

DATA_WIDTH

4 or 8

8

Decimal

Defines the parallel-to-serial data converter width.

INIT

1 or 0

0

Binary

Initializes the OSERDESE3 flip-flops to the value specified.

ODDR_MODE

TRUE/FALSE

FALSE

String

Internal property set by the Vivado tools when using ODDRE1. Do not modify. Forces the OSERDESE3 into an ODDRE1 mode with a 3-state ODDRE1 flip-flop as shown in This Figure. In the ODDRE1 mode, data is connected to D[4,0] and the clock must be connected to CLKDIV (UltraScale devices) or CLK (UltraScale+ devices). The ODDRE1 primitive is recommended.

OSERDES_D_BYPASS

TRUE/FALSE

FALSE

String

When TRUE, D[0] is passed onto OQ.

When FALSE, serialized D[0] and D[4] is output on OQ.

OSERDES_T_BYPASS

TRUE/FALSE

FALSE

String

When TRUE, D[1] is passed onto T_OUT.

When FALSE, serialized D[1] and D[5] is output on T_OUT.

IS_CLK_INVERTED

1 or 0

0

Bit

Sets a local clock inversion for CLK input when 1.

IS_CLKDIV_INVERTED

1 or 0

0

Bit

Sets a local clock inversion for CLKDIV input when 1.

IS_RST_INVERTED

1 or 0

0

Bit

Sets a local inversion for RST input when 1.

SIM_DEVICE

ULTRASCALE, ULTRASCALE_PLUS, ULTRASCALE_PLUS_ES1, ULTRASCALE_PLUS_ES2

ULTRASCALE

String

Device family for behavioral simulation.