RIU Ports

UltraScale Architecture SelectIO Resources User Guide (UG571)

Document ID
UG571
Release Date
2022-08-31
Revision
1.14 English

Table: RIU Ports lists register interface unit ports.

Table 2-38:      RIU Ports

Pins

I/O

Type

Description

RIU_CLK

Input

Clock

Clock from interconnect logic.

Clock for the RIU interface peripheral.

This clock is independent of all other clocks of the BITSLICE_CONTROL.

The RIU clock needs to be connected when BISC is enabled.

RIU_ADDR[5:0]

Input

Data

Register address.

The address input bus provides a register address for the register interface.

The address value on this bus specifies the configuration bits that are written or read with the next RIU_CLK cycle. When not used, all bits must be assigned zeros.

RIU_WR_DATA[15:0]

Input

Data

Data write to register.

This input bus provides data. The value of this bus is written to the configuration cells of the register interface. The data is presented in the cycle that RIU_WR_EN and RIU_NIBBLE_SEL are active. The data is captured in a shadow register and written at a later time.

RIU_VALID indicates when the RIU port is ready to accept another write. When not used, all bits must be set to zero.

RIU_RD_DATA[15:0]

Output

Data

Data read from register.

This output bus provides RIU data.

The value of this bus is a representation of the register bits addressed by RIU_ADDR. See Register Definitions and Addresses.

The data is presented in the next cycle when RIU_NIBBLE_SEL is active and RIU_WR_EN is 0.

When not used, this output bus must be left floating.

RIU_VALID

Output

Data

Status indicating if BISC is accessing RIU registers.

This signal indicates the status when RIU accesses are made from the interconnect logic while the internal BISC state machines also are accessing the RIU registers.

During a collision (i.e., an RIU write access occurs during a BISC write access), the RIU_VALID signal is deasserted. The interconnect logic write access still succeeds, but not until RIU_VALID is asserted. No further action is required on the interconnect logic side, except that no further RIU accesses are possible until RIU_VALID is asserted. In addition to collisions, the RIU_VALID deasserts when writing to the RL_DLY_RNK0, RL_DLY_RNK1, RL_DLY_RNK2, or RL_DLY_RNK3 registers. These registers are unique because it takes more than two cycles for an RIU write to update them. Therefore back-to-back accesses to these registers are impossible.

RIU_WR_EN

Input

Enable

Register write enable (active-High).

This signal and RIU_NIBBLE_SEL must be asserted High to write a register in an RIU interface.

RIU_NIBBLE_SEL

Input

Data

Nibble in byte select.

An I/O bank is constructed from four bytes. Each byte contains two nibbles. Each nibble contains a BITSLICE_CONTROL component for control of all RX or TX BITSLICEs of the nibble. This signal is used to select a nibble RIU in a byte.