RIU Read Actions

UltraScale Architecture SelectIO Resources User Guide (UG571)

Document ID
UG571
Release Date
2022-08-31
Revision
1.14 English

In the RIU read, data from the RIU is driven out on the RIU_RD_DATA bus that depends on RIU_ADDR and the RIU_NIBBLE_SEL signal (This Figure). When RIU_NIBLE_SEL is asserted, data is presented one clock cycle later on the RIU_RD_DATA bus.

Figure 2-78:      RIU Read

X-Ref Target - Figure 2-78

X16044-riu-read.jpg

This Figure shows a back to back write and read operation.

Figure 2-79:      RIU Read Modify Write

X-Ref Target - Figure 2-79

X16045-riu-read-modify-write.jpg

In This Figure, registers Nibble_Ctrl0 (0x00) and Nibble_Ctrl1 (0x01) are accessed. RIU_RD_DATA is shown as 0x0000, 0x002D, and 0x00D7 during read and write cycles and the content of the RIU_WR_DATA bus is 0xE739. The contents of register Nibble_Ctrl1 shows 0x0739 after two cycles of latency and the data appears on the RIU_RD_DATA bus with one clock cycle latency.