In the RIU read, data from the RIU is driven out on the RIU_RD_DATA bus that depends on RIU_ADDR and the RIU_NIBBLE_SEL signal (This Figure). When RIU_NIBLE_SEL is asserted, data is presented one clock cycle later on the RIU_RD_DATA bus.
This Figure shows a back to back write and read operation.
In This Figure, registers Nibble_Ctrl0 (0x00) and Nibble_Ctrl1 (0x01) are accessed. RIU_RD_DATA is shown as 0x0000, 0x002D, and 0x00D7 during read and write cycles and the content of the RIU_WR_DATA bus is 0xE739. The contents of register Nibble_Ctrl1 shows 0x0739 after two cycles of latency and the data appears on the RIU_RD_DATA bus with one clock cycle latency.