A RIU register write action to a RIU register is when RIU_WR_EN, RIU_NIBBLE_SEL, and RIU_ADDR are asserted (This Figure). The data is written into the RIU registers two clocks after RIU_WR_EN. Interconnect logic can issue RIU write only when RIU_RD_VALID is High.
Writing to the RIU registers requires the RIU logic to arbitrate between BISC accesses and access from the interconnect logic. BISC access to RIU registers always has precedence over interconnect logic access, hence an interconnect logic transaction is stored and resumed after BISC access.