RXTX_BITSLICE

UltraScale Architecture SelectIO Resources User Guide (UG571)

Document ID
UG571
Release Date
2022-08-31
Revision
1.14 English

This basic primitive can be used as receiver, transmitter, or bidirectional circuit. This primitive is the base from which the RX_BITSLICE and TX_BITSLICE are generated.

The RXTX_BITSLICE contains both an input and output path. Included in the input and output paths are input and output delays that can be continuously corrected for VT variation by BITSLICE_CONTROL, serialization logic for either 4:1 or 8:1 on the output path, and deserialization logic for 1:4 or 1:8 on the input path. The input path also includes a shallow FIFO to allow connection of received data to another clock domain in the general interconnect logic. A block diagram of RXTX_BITSLICE is shown in This Figure.

Figure 2-32:      RXTX_BITSLICE Block Diagram

X-Ref Target - Figure 2-32

X16329-rxtx_bitslice-block-diagram.jpg