RXTX_BITSLICE Attributes

UltraScale Architecture SelectIO Resources User Guide (UG571)

Document ID
UG571
Release Date
2023-08-31
Revision
1.15 English

Table: RXTX_BITSLICE Attributes lists the RXTX_BITSLICE attributes.

Table 2-23: RXTX_BITSLICE Attributes

Attributes

Values

Default

Type

Description

RX_DATA_TYPE

DATA DATA_AND_CLOCK SERIAL

DATA

String

Attribute defining the type of signal BITSLICE is receiving (DATA, DATA_AND_CLOCK, or SERIAL) and the capture clock to be used.

SERIAL = When received data must be captured by an unrelated clock (for example SGMII).

DATA_AND_CLOCK = When the received signal is either clock/strobe or data. When the received clock/strobe must be sampled as if it is data.

DATA = When the received signal contains purely data information.

DATA_AND_CLOCK is only used for bit slices positioned at DBC, QBC or GC pins (bitslice_0).

DATA can be used for all bit slices in a nibble when the received signal contains pure data information.

RX_DATA_WIDTH

4 or 8

8

Decimal

Note: Since BITSLICE_CONTROL.DIV_MODE must match the data width, TX_DATA_WIDTH and RX_DATA_WIDTH must be same.

Attribute defining the output width of the serial-to-parallel converter.

This specifies the width that the incoming data is expanded to in the serial-to-parallel converter (deserialization), and it should match the DIV_MODE clock division setting of the corresponding BITSLICE_CONTROL as shown in this table:

RXTX_BITSLICE DATA_WIDTH

BITSLICE_
CONTROL DIV_MODE

4

2

8

4

RX_DELAY_FORMAT

TIME (1) or COUNT

TIME

String

Note: For BISC to properly align RXTX_BITSLICEs, set TX_DELAY_FORMAT= RX_DELAY_FORMAT.

DELAY_FORMAT can be either TIME or COUNT.

When set to TIME, the input delay equals DELAY_VALUE (specified in ps) plus an additional alignment delay (Align_Delay) after BISC completes (DLY_RDY goes HIGH).

BISC uses the RX_REFCLK_FREQUENCY attribute in conjunction with the incoming master clock to determine how many taps are required to achieve the requested TIME value (RX_DELAY_VALUE). This calibration accounts for the process variation in the device.

When set to COUNT, the value given in RX_DELAY_VALUE is the number of taps required.

RX_DELAY_TYPE

FIXED

VAR_LOAD

VARIABLE

FIXED

String

Delay mode of the input delay line. For more information, see Native Input Delay Type Usage .

RX_DELAY_VALUE

0–1250 (TIME UltraScale)

0–1100 (TIME UltraScale+)

0–511 (COUNT)

0

Decimal

Note: For BISC to properly align, set RX_CLK_PHASE_P = RX_CLK_PHASE_N = SHIFT_0.

TIME mode: Desired value in ps.

UltraScale devices support delays up to 1.25 ns.

UltraScale+ devices support up to 1.1 ns.

COUNT mode: Desired value in taps. To ensure TX_BITSLICE data alignment, limit COUNT delays to 1.5 UI.

For more information, see Native Input Delay Type Usage .

TX_DATA_WIDTH

4 or 8

8

Decimal

Since BITSLICE_CONTROL.DIV_MODE must match the data width, TX_DATA_WIDTH and RX_DATA_WIDTH must be same.

Attribute defining the input width of the parallel-to-serial converter.

TX_DATA_WIDTH = 2 x BITSLICE_CONTROL.DIV_MODE

TX_DELAY_FORMAT

TIME (1) or COUNT

TIME

String

Note: For BISC to properly calibrate RXTX_BITSLICEs, set TX_DELAY_FORMAT=
RX_DELAY_FORMAT.

TX_DELAY_FORMAT can be either TIME or COUNT.

When set to TIME, the delay after BISC completes (DLY_RDY goes High) equals the delay given in TX_DELAY_VALUE (specified in ps).

BISC uses the TX_REFCLK_FREQUENCY attribute in conjunction with the incoming master clock to determine how many taps are required to achieve the requested TIME value (TX_DELAY_VALUE). This calibration accounts for the process variation in the device.

When set to COUNT, the value given in TX_DELAY_VALUE is the number of taps required.

TX_DELAY_TYPE

FIXED

VAR_LOAD

VARIABLE

FIXED

String

Delay mode of the output delay line.

For further information, see Native Output Delay Type Usage .

TX_DELAY_VALUE

0–1250 (TIME UltraScale)

0–1100 (TIME UltraScale+)

0–511 (COUNT)

0

Decimal

Note: For BISC to properly calibrate RXTX_BITSLICEs, set TX_DELAY_VALUE=
RX_DELAY_VALUE and TX_OUTPUT_PHASE_90 = FALSE.

TIME mode: Desired value of the delay line in ps.

UltraScale devices support delays up to 1.25 ns.

UltraScale+ devices support up to 1.1 ns.

COUNT mode: Desired value of the delay line in taps. To ensure TX_BITSLICE data alignment, limit COUNT delays to 1.5 UI.

RX_REFCLK_FREQUENCY

200.00–2400.00 (UltraScale)

300.00–2666.67 (UltraScale+)

300.0

1 significant digit float

Note: Since there is only a single reference clock for BITSLICE_CONTROL, set TX_REFCLK_FREQUENCY = RX_REFCLK_FREQUENCY.

Specification of reference clock frequency in MHz.

This is the frequency of the master clock, PLL_CLK, the BITSLICE_CONTROL uses. This master clock is used by BISC to calibrate any TIME mode delays. The tap size is not determined by the RX_REFCLK_FREQUENCY. The tap size is defined in the UltraScale device data sheets as TIDELAY_RESOLUTION [Ref 2] .

The RX_REFCLK_FREQUENCY attribute along with the requested delay, RX_DELAY_VALUE, is used by BISC to calibrate the amount of taps to provide the requested delay of RX_DELAY_VALUE when RX_DELAY_FORMAT is set to TIME mode.

TX_REFCLK_FREQUENCY

200.00–2400.00 (UltraScale)

300.00–2666.67 (UltraScale+)

300.0

1 significant digit float

Note: Since there is only a single reference clock for BITSLICE_CONTROL, set TX_REFCLK_FREQUENCY = RX_REFCLK_FREQUENCY.

Specification of reference clock frequency in MHz.

This is the frequency of the master clock, PLL_CLK, the BITSLICE_CONTROL uses. This master clock is used by BISC to calibrate any TIME mode delays (Refer to native mode clocking/BISC sections). The tap size is not determined by the TX_REFCLK_FREQUENCY. The tap size is defined in the UltraScale device data sheets as TIDELAY_RESOLUTION [Ref 2] .

The TX_REFCLK_FREQUENCY attribute along with the requested delay, TX_DELAY_VALUE, is used by BISC to calibrate the amount of taps to provide the requested delay when TX_DELAY_FORMAT is set to TIME mode.

RX_UPDATE_MODE

ASYNC, SYNC, or MANUAL

ASYNC

String

ASYNC: This is the default and preferred use method.

Updates to the delay value are independent of the data being received.

This mode is the preferred operation mode because it covers the function of both other modes, too.

SYNC: updates require DATAIN transitions to synchronously update the delay with the DATAIN edges. This mode is suitable for clocks or data that are always available and switches on a periodic basis.

MANUAL: It takes two assertions of LOAD for the new value to take effect. The first LOAD loads the value defined by CNTVALUEIN and the second LOAD must be asserted with an assertion of the CE for the new value to take effect. This is beneficial because you can update the delay when the data becomes idle.

TX_UPDATE_MODE

ASYNC, SYNC, or MANUAL

ASYNC

String

ASYNC: This is the default and preferred use method.

Updates to the delay value are independent of the data being received.

This mode is the preferred operation mode because it covers the function of both other modes, too.

SYNC: Updates require DATAIN transitions to synchronously update the delay with the DATAIN edges. This mode is suitable for clocks or data that are always available and switches on a periodic basis.

MANUAL: It takes two assertions of LOAD for the new value to take effect. The first LOAD loads the value defined by CNTVALUEIN and the second LOAD must be asserted with an assertion of the CE for the new value to take effect. This is beneficial because you can update the delay when the data becomes idle.

FIFO_SYNC_MODE

TRUE or FALSE

FALSE

BOOLSTRING

Attribute defining the relationship between FIFO_WRCLK_OUT and FIFO_RD_CLK. Always set this attribute to FALSE.

FIFO_SYNC_MODE = TRUE. Reserved for later use.

See the Clocking in Native Mode in the BITSLICE_CONTROL section for more information on these clocks.

INIT

1'b0 or 1'b1

1'b1

Binary

Defines the initial value of the serialized data output of the RXTX_BITSLICE/TX_BITSLICE.

LOOPBACK

TRUE or FALSE

FALSE

BOOLSTRING

FALSE: RXTX_BITSLICE has distinct input (DATAIN) and/or output (O) to the input or output of bidirectional buffers in the IOB.

TRUE: The output O is looped back to the DATAIN. This loopback is achieved inside the RXTX_BITSLICE by connecting the output delay output to the input delay input. The delay lines are thus part of the loopback cycle.

TBYTE_CTL

TBYTE_IN or T

TBYTE_IN

Decimal

TBYTE_IN: The BITSLICE_CONTROL.TBYTE_IN[3:0] input is used to pass the 3-state information to the T_OUT output. This requires that the RXTX_BITSLICE/TX_BITSLICE is used together with a TX_BITSLICE_TRI.

T: The T input is used to pass the 3-state information from logic to the T_OUT output. T requires that the 3-state information is generated in the logic.

TX_OUTPUT_PHASE_90

TRUE or FALSE

FALSE

String

FALSE: Output of RXTX_BITSLICE/TX_BITSLICE is not phase-shifted.

TRUE: Output of RXTX_BITSLICE/TX_BITSLICE is phase-shifted 90 degrees.

RX_DELAY_VALUE/ TX_DELAY_VALUE must be set to 0 when TX_OUTPUT_PHASE_90 =TRUE.

The phase shift can easily be observed when different transmitters are used. This attribute is most used to shift the generated clock 90 degrees to the generated data.

ENABLE_PRE_EMPHASIS

TRUE or FALSE

FALSE

String

Used in conjunction with attributes on the bidirectional IOB to enable and disable pre-emphasis.

Pre-emphasis is documented in Transmitter Pre-Emphasis .

IS_RX_CLK_INVERTED

1'b0 or 1'b1

1'b0

Binary

When 1 reverses polarity (inverts) the RX_CLK signal.

Similar to the IS_RX_RST_INVERTED attribute but on the RX_CLK path.

When IS_RX_CLK_INVERTED = 1, the inverter is used.

When IS_RX_CLK_INVERTED = 0, the inverter is not used.

IS_RX_RST_DLY _INVERTED

1'b0 or 1'b1

1'b0

Binary

When 1 reverses polarity (inverts) the RX_RST_DLY signal.

Similar to the IS_RX_RST_INVERTED attribute but on the RX_RST_DLY path.

When IS_RX_RST_DLY_INVERTED = 1, the inverter is used.

When IS_RX_RST_DLY_INVERTED = 0, the inverter is not used.

IS_RX_RST_INVERTED

1'b0 or 1'b1

1'b0

Binary

When 1 reverses polarity (inverts) the RX_RST signal.

A selectable local inverter on the reset path that can change the polarity of the reset input.

When IS_RX_RST_INVERTED = 1, the inverter is used.

When IS_RX_RST_INVERTED = 0, the inverter is not used.

IS_TX_CLK_INVERTED

1'b0 or 1'b1

1'b0

Binary

When 1 reverses polarity (inverts) the TX_CLK signal.

This attribute is similar to the IS_RX_RST_INVERTED attribute but on the TX_CLK path.

When IS_TX_CLK_INVERTED = 1, the inverter is used.

When IS_TX_CLK_INVERTED = 0, the inverter is not used.

IS_TX_RST_DLY _INVERTED

1'b0 or 1'b1

1'b0

Binary

When 1 reverses polarity (inverts) the TX_RST_DLY signal.

Similar to the IS_RX_RST_INVERTED attribute but on the TX_RST_DLY path.

When IS_TX_RST_DLY_INVERTED = 1, the inverter is used.

When IS_TX_RST_DLY_INVERTED = 0, the inverter is not used.

IS_TX_RST_INVERTED

1'b0 or 1'b1

1'b0

Binary

When 1 reverses polarity (inverts) the TX_RST signal.

A selectable local inverter on the reset path that can change the polarity of the reset input.

When IS_TX_RST_INVERTED = 1, the inverter is used.

When IS_TX_RST_INVERTED = 0, the inverter is not used.

NATIVE_ODELAY_BYPASS

TRUE or FALSE

FALSE

String

When TRUE, bypass the ODELAY.

UltraScale+ FPGAs only: Reserved for memory interface generator (MIG). When TRUE, bypass the ODELAY.

SIM_DEVICE

Possible Values: ULTRASCALE, ULTRASCALE_PLUS, ULTRASCALE_PLUS_ES1, ULTRASCALE_PLUS_ES2

ULTRASCALE

String

Sets the device version (ULTRASCALE, ULTRASCALE_PLUS, ULTRASCALE_PLUS_ES1, ULTRASCALE_PLUS_ES2)

Notes:

1. When in TIME mode, calibration will affect the availability of bit slices within the nibble. See Bank Overview for more information.