RXTX_BITSLICE Ports

UltraScale Architecture SelectIO Resources User Guide (UG571)

Document ID
UG571
Release Date
2022-08-31
Revision
1.14 English

The RXTX_BITSLICE primitive is shown in This Figure. In this figure, black represents inputs and gray represents outputs. Table: RXTX_BITSLICE Ports lists the RXTX_BITSLICE ports.

Figure 2-45:      RXTX_BITSLICE Primitive

X-Ref Target - Figure 2-45

X16036-rxtx_bitslice-primitive.jpg

Table: RXTX_BITSLICE Ports lists the RXTX_BITSLICE ports.

Table 2-22:      RXTX_BITSLICE Ports

Port

Function(1)

I/O

Synchronous Clock Domain

Description

DATAIN

I/O

RX

Input

Asynchronous

This is the input signal from the IOB. When a differential input buffer is used with a single output (example IBUFDS), the RX_BITSLICE adjacent to the P-side of the differential pair is used. If a differential input buffer with complementary outputs (example IBUFDS_DIFF_OUT) is used, adjacent RX_BITSLICEs for both the P and N inputs are used.

The incoming signal from the IOB can be data, clock, or strobe, selected by the DATA_TYPE attribute on the RX_BITSLICE.

When configured as either a clock or both clock and data, DATAIN is the incoming strobe/clock being forwarded through the RX_BITSLICE and to the BITSLICE_CONTROL to create the clock to the other RX_BITSLICEs to capture data. This strobe/clock bit slice must be positioned on a QBC or DBC IOB site, which is always located at bit slice position zero in a nibble. See the Clocking in Native Mode in the BITSLICE_CONTROL section for more information.

When the incoming signal from the IOB is data only, it can be located at any bit slice position in the nibble.

Q[7:0]

RX

FPGA

Output

FIFO_RD_CLK

Deserialized (parallel) output data from the RX FIFO goes to the interconnect logic.

If the DATA_WIDTH = 4, Q[3:0] outputs the captured data. Q[7:4] can be left unconnected and Q5 represents the serial data stream arriving at DATAIN.

Note:   For BITSLICE 0 and 6 (upper nibble BITSLICE 0), the route through from DATAIN to Q5 can only be used after DLY_RDY is asserted.

If DATA_WIDTH = 8, Q[7:0] represent 8 bits of captured serial data, and route through from DATAIN to Q5 is not available.

RX_RST

RX

FPGA

Input

Asynchronous

Resets the receive side (RX_BITSLICE) logic, asynchronous assertion and synchronous deassertion and is active-High. Q resets to zero while RST is asserted.

See Native Mode Bring-up and Reset for more information.

RX_CLK

RX

FPGA

Input

Asynchronous

Delay line clock used to control RX_LOAD, RX_CE and RX_INC. All control inputs to delay line element within the receiver logic are synchronous to the clock input (RX_CLK). A clock must be connected to this port when the delay is configured in VARIABLE or VAR_LOAD. RX_CLK can be locally inverted and must be supplied by a global clock buffer.

RX_CE

RX

FPGA

Input

RX_CLK

Clock enable for the delay line register lock.

RX_RST_DLY

RX

FPGA

Input

Asynchronous (synchronously deassert to RX_CLK)

Reset port for the delay line component within the receiver logic. Resets the internal delay line to the value defined in RX_DELAY_VALUE.

RX_INC

RX

FPGA

Input

RX_CLK

The increment/decrement is controlled by the enable signal (RX_CE). This interface is only available when the delay line is in VARIABLE or VAR_LOAD mode. As long as CE remains High, the delay line is incremented or decremented by one tap every clock (RX_CLK) cycle. The state of RX_INC determines whether delay line is incremented or decremented: RX_INC = 1 increments; RX_INC = 0 decrements, synchronously to the clock (RX_CLK). If RX_CE is Low, the delay through the delay line does not change (regardless of the state of RX_INC).

The programmable delay taps in the delay line wraps around. When the last tap delay is reached (RX_CNTVALUEOUT = 511), a subsequent increment function returns to tap 0. The same applies to the decrement function: decrementing from zero moves to tap 511.

RX_LOAD

RX

FPGA

Input

RX_CLK

When in VAR_LOAD mode and RX_UPDATE_MODE=ASYNC, the delay line load port, RX_LOAD, loads the value set by the RX_CNTVALUEIN into the delay line. The value present at RX_CNTVALUEIN[8:0] is the new tap value. The RX_LOAD signal is an active-High signal and is synchronous to the input clock signal (RX_CLK). Wait at least one RX_CLK clock cycle after applying a new value on the RX_CNTVALUEIN bus before applying the LOAD signal. RX_CE must be held Low during RX_LOAD operation.

RX_EN_VTC

RX

FPGA

Input

Asynchronous

Enable Voltage, temperature, and process calibration/compensation.

High: Allows BITSLICE_CONTROL to keep delay constant over VT. BITSLICE_CONTROL.EN_VTC must be HIGH for VT compensation to be enabled.

Low: VT compensation is disabled.

When TIME mode is used, the RX_EN_VTC signal must be pulled High during initial built-in self-calibration (BISC).

When COUNT mode is used, the RX_EN_VTC signal must be pulled Low.

When bit slices are used in both TIME and COUNT mode in a nibble, RX_EN_VTC must be pulled High for the bit slices used in TIME mode, and must be pulled Low for those used in COUNT mode.

RX_CNTVALUEIN[8:0]

RX

FPGA

Input

RX_CLK

The RX_CNTVALUEIN bus is used to dynamically change the loadable tap value. The 9-bit value at the RX_CNTVALUEIN is the number of taps required. New RX_CNTVALUEIN values should only be applied when RX_EN_VTC is Low. Apply new RX_CNTVALUIN one clock cycle before RX_LOAD pulse.

The new value is best applied one clock cycle before applying the LOAD signal. The delay line can be changed from 1 to 8 taps at a time.

RX_CNTVALUEOUT[8:0]

RX

FPGA

Output

RX_CLK

The RX_CNTVALUEOUT pins are used for reporting the current tap value, and reads out the amount of taps in the current delay. When RX_EN_VTC is High, RX_CNTVALUEOUT is updated by the BITSLICE_CONTROL.

FIFO_RD_CLK

RX

FPGA

Input

Asynchronous

The deserialized received data is read from the FIFO using the FIFO_RD_CLK signal. The FIFO read clock can be generated by PLL/MMCM or come from the FIFO_WRCLK_OUT output.

Read FIFO Function for more information.

FIFO_RD_EN

RX

FPGA

Input

FIFO_RD_CLK

Enables a read operation from the RX FIFO, active-High. When this signal is Low, the FIFO read pointer is held at the same position. The effect of this is that the Q-output shows new data every eight clock cycles. See FIFO Function.

FIFO_EMPTY

RX

FPGA

Output

FIFO_RD_CLK

FIFO empty flag for this bit. When the FIFO write pointer and read pointer are the same, this signal is High.

When inverted and registered, connect FIFO_EMPTY to FIFO_RD_EN to obtain a continuous data stream from the FIFO.

FIFO_WRCLK_OUT

RX

FPGA

Output

PLL_CLK (for SERIAL_MODE)

or DQS_IN (for source synchronous interfaces)

(BITSLICE_CONTROL)

This signal is only valid for a bit slice positioned at BITSLICE 0 of a nibble. These pins for bit slices in other positions have no routing in the FPGA.

The FIFO_WRCLK_OUT is a copy of the bit slice internal FIFO_WR_CLK. It is a divided version of the data sample clock/strobe. This clock writes the deserialized parallel data in the bit slice into the FIFO.

Note:   The use of this port is only recommended for experienced designers.

Additional timing constraints are described in FIFO Function.

D[7:0]

TX

FPGA

Input

PLL_CLK

(BITSLICE_CONTROL)

Parallel incoming data from interconnect logic for transmit. Width is determined by the TX_DATA_WIDTH attribute and can be either 8 or 4. If the TX_DATA_WIDTH is 4, D[3:0] is used and D[7:4] should be tied to 0.

T

TX

FPGA

Input

Asynchronous

T assigns a combinatorial path through the TX_BITSLICE to the 3-state pin of an output buffer.

When the 3-state control is sourced from the interconnect logic, the T port must be used. Use of the T input of a bit slice can be seen as a block 3-state of the serial bitstream.

Each TX_BITSLICE in a nibble has a T input, meaning that there are 13 T inputs for a byte (byte = two nibbles)

TBYTE_IN

TX

FPGA

Input

PLL_CLK

(BITSLICE_CONTROL)

The TBYTE_IN is 1-bit wide input of the TX_BITSLICE side of the RXTX_BITSLICE. When using this 3-state, the TX_BITSLICE_TRI component must be used to serialize the TBYTE_IN[3:0] 3-state bus input of the BITSLICE_CONTROL, giving the ability to 3-state individual bits in the serial output data stream. The TBYTE_IN[3:0] port of the BITSLICE_CONTROL is handled and passes through the BITSLICE_CONTROL to connect to the TX_BITSLICE_TRI. The TRI_OUT (TX_BITSLICE_TRI) then connects to each TBYTE_IN (TX_BITSLICE) input. A logic High means the data is not 3-stated and a logic Low means the data is 3-stated.

O

I/O

TX

Output

PLL_CLK

(BITSLICE_CONTROL)

Serialized output data from the TX_BITSLICE that should be connected to the output buffer (or bidirectional buffer).

T_OUT

I/O

TX

Output

PLL_CLK (when TBYTE_CTL set to TBYTE_IN)

otherwise Asynchronous

(BITSLICE_CONTROL)

3-state output from the TX_BITSLICE that should be connected to the output buffer (or bidirectional buffer). The output can be either the combinatorial output when TBYTE_CTL is set to T or the serialized output when TBYTE_CTL is set to TBYTE_IN.

TX_RST

TX

FPGA

Input

Asynchronous

Resets the transmit side (TX_BITSLICE), asynchronous assertion and synchronous deassertion and is active-High. O resets to the INIT attribute value while RST is asserted.

For deterministic bring-up, follow the steps in Native Mode Bring-up and Reset.

TX_CLK

TX

FPGA

Input

Asynchronous

Delay line clock used to sample TX_LOAD, TX_CE, and TX_INC. All control inputs to output delay line element within the TX part of the RXTX_BITSLICE are synchronous to the clock input (TX_CLK). A clock must be connected to this port when the delay is configured in VARIABLE or VAR_LOAD. The TX_CLK can be locally inverted, and must be supplied by a global clock buffer.

TX_CE

TX

FPGA

Input

TX_CLK

Clock enable for the output delay line register clock.

TX_RST_DLY

TX

FPGA

Input

Asynchronous

(synchronously deassert to TX_CLK)

Reset port for the delay line component within the transmit logic. Resets the internal delay line to the value defined in the TX_DELAY_VALUE attribute.

TX_INC

TX

FPGA

Input

TX_CLK

The increment/decrement is controlled by the enable signal (TX_CE). This interface is only available when the delay line is in VARIABLE or VAR_LOAD mode. As long as TX_CE remains High, the delay line is incremented or decremented by one tap every clock (TX_CLK) cycle. The state of TX_INC determines whether the delay line is incremented or decremented: TX_INC = 1 increments; TX_INC = 0 decrements, synchronously to the clock (TX_CLK). If TX_CE is Low, the delay through the delay line does not change (regardless of the state of TX_INC). When TX_CE goes High, the increment/decrement operation begins on the next positive clock edge. When TX_CE goes Low, the increment/decrement operation ceases on the next positive clock edge.

The programmable delay taps in the delay line primitive wrap around. When the last tap delay is reached (TX_CNTVALUEOUT = 511), a subsequent increment function returns to tap 0. The same applies to the decrement function: decrementing from zero moves to tap 511.

TX_LOAD

TX

FPGA

Input

TX_CLK

When in VAR_LOAD mode, this input loads the value set by the TX_CNTVALUEIN into the delay line and TX_UPDATE_MODE = ASYNC. The value present at TX_CNTVALUEIN[8:0] is the new tap value. The TX_LOAD signal is an active-High signal and is synchronous to the input clock signal (TX_CLK). The TX_CE must be held Low during TX_LOAD operation.

TX_EN_VTC

TX

FPGA

Input

Asynchronous

Enable voltage, temperature, and process compensation.

High: Allows BITSLICE_CONTROL to keep delay constant over VT. BITSLICE_CONTROL.EN_VTC must be High for VT compensation to be enabled.

Low: VT compensation is disabled.

When TIME mode is used, the TX_EN_VTC signal must be pulled High during initial BISC.

When used in COUNT mode, the TX_EN_VTC signal must be pulled Low.

When bit slices are used in both COUNT and TIME mode in a nibble, TX_EN_VTC must be pulled High for the bit slices used in TIME mode, and pulled Low for those used in COUNT mode.

TX_CNTVALUEIN[8:0]

TX

FPGA

Input

TX_CLK

The TX_CNTVALUEIN bus is used for dynamically changing the loadable tap value. The 9-bit value at the TX_CNTVALUEIN bus is the new tap value the delay line is set to after TX_LOAD. Provide the value on this bus at least one clock cycle before TX_LOAD. The delay line can be changed from 1 to 8 taps at a time.

Note:   For VT compensation, the RXTX_BITSLICE only compensates for the input delay value when using TX_EN_VTC. Applications requiring the output delay to be compensated for require the input delay to match the output delay.

TX_CNTVALUEOUT[8:0]

TX

FPGA

Output

TX_CLK

The TX_CNTVALUEOUT pins are used for reporting the current tap value, and read out the amount of taps in the current delay. When TX_EN_VTC is High, TX_CNTVALUEOUT is updated by the BITSLICE_CONTROL.

The following RX/TX_BIT_CTRL_OUT and RX/TX_BIT_CTRL_IN pins are 40-bit bus connections between the RXTX_BITSLICE (RX_BITSLICE and/or TX_BITSLICE) and the BITSLICE_CONTROL. Each of these 40-bit buses carry data, clocks, RIU, and status signals between the RXTX_BITSLICE (RX_BITSLICE, TX_BITSLICE), TX_BITSLICE_TRI, and BITSLICE_CONTROL and vice versa.

When a bit slice is used, these buses must be connected to the appropriate BITSLICE_CONTROL input and output bus.

Example:

When RXTX_BITSLICE_2 is used, RX/TX_BIT_CTRL_OUT of that RXTX_BITSLICE must connect to the BITSLICE_CONTROL RX/TX_BIT_CTRL_IN2, and the RX/TX_BIT_CTRL_IN of the RXTX_BITSLICE buses must connect to the BITSLICE_CONTROL RX/TX_BIT_CTRL_OUT2 buses.

These buses are made of dedicated routing between the BITSLICE_CONTROL and bit slices and cannot be accessed or used by logic in the FPGA. It is also not possible to connect an ILA or VIO to these buses and viewing the buses in simulation is meaningless because the content and bit names of the buses is not disclosed.

RX_BIT_CTRL_IN[39:0]

 

Input

N/A

Input bus from BITSLICE_CONTROL

RX_BIT_CTRL_OUT[39:0]

 

Output

N/A

Output bus to BITSLICE_CONTROL

TX_BIT_CTRL_IN[39:0]

 

Input

N/A

Input bus from BITSLICE_CONTROL

TX_BIT_CTRL_OUT[39:0]

 

Output

N/A

Output bus to BITSLICE_CONTROL

Notes:

1.I/O RX: Connections between the RX_BITSLICE side of the RXTX_BITSLICE and the I/O buffers.
I/O TX: Connections between the TX_BITSLICE side of the RXTX_BITSLICE and the I/O buffers.
RX FPGA: Connections from/to the RX_BITSLICE side of the RXTX_BITSLICE and the FPGA logic.
TX FPGA: Connections from/to the TX_BITSLICE side of the RXTX_BITSLICE and the FPGA logic.