RX_BITSLICE

UltraScale Architecture SelectIO Resources User Guide (UG571)

Document ID
UG571
Release Date
2022-08-31
Revision
1.14 English

The RX_BITSLICE is the receiver of the RXTX_BITSLICE. For all receive interfaces, RXTX_BITSLICE can be used except where CASCADE delay is needed. RX_BITSLICE allows the two delay lines in the bit slice to be cascaded for a large delay.

Like the RXTX_BITSLICE, the RX_BITSLICE contains an input delay that can continuously be corrected for VT variation by the BITSLICE_CONTROL. High-speed capture registers, deserialization logic for either 1:4 or 1:8, and a shallow FIFO allow easy connection to another clock domain. A block diagram of RX_BITSLICE is shown in This Figure.

Note:   The input buffer is not part of the RX_BITSLICE.

Figure 2-47:      RX_BITSLICE Block Diagram

X-Ref Target - Figure 2-47

X16026-rx_bitslice-block-diag.jpg

The RX_BITSLICE primitive is shown in This Figure. In this figure, black represents inputs and gray represents outputs. Table: RX_BITSLICE Ports lists the RXTX_BITSLICE ports.

Figure 2-48:      RX_BITSLICE Primitive

X-Ref Target - Figure 2-48

X16027-rx_bitslice-primitive.jpg