RX_BITSLICE Attributes

UltraScale Architecture SelectIO Resources User Guide (UG571)

Document ID
UG571
Release Date
2022-08-31
Revision
1.14 English

Table: RX_BITSLICE Attributes lists the RX_BITSLICE attributes.

Table 2-25:      RX_BITSLICE Attributes

Attributes

Values

Default

Type

Description

DATA_TYPE

DATA

DATA_AND_CLOCK

SERIAL

DATA

String

SERIAL = When received data must be captured by a unrelated clock (for example, SGMII).

DATA_AND_CLOCK = When the received signal is either clock/strobe or data. When the received clock/strobe must be sampled as if it is data.

DATA = When the received signal contains purely data information.

DATA_AND_CLOCK is only used for bit slices positioned at DBC, QBC or GC pins (BITSLICE_0).

DATA can be used for all bit slices in a nibble when the received signal contains pure data information.

DATA_WIDTH

4 or 8

8

Decimal

Attribute defining the output width of the serial-to-parallel converter.

This specifies the width that the incoming data is expanded to in the serial-to-parallel converter (deserialization), and it should match the DIV_MODE clock division setting of the corresponding BITSLICE_CONTROL as shown in this table:

RX_BITSLICE DATA_WIDTH

BITSLICE_CONTROL DIV_MODE

4

2

8

4

DELAY_FORMAT

TIME(1) or COUNT

TIME

String

DELAY_FORMAT can be either TIME or COUNT.

When set to TIME, the delay will be equal to DELAY_VALUE (specified in ps) plus an additional alignment delay (Align_Delay) after BISC completes (DLY_RDY goes HIGH).

BISC uses the REFCLK_FREQUENCY attribute in conjunction with the incoming master clock to determine the current tap size and therefore how many taps are required to achieve the requested TIME value (DELAY_VALUE). This calibration accounts for the process variation in the device. When EN_VTC is High, the delay is calibrated to provide the requested TIME across voltage and temperature.

When set to COUNT, the value given in DELAY_VALUE is the number of taps required. EN_VTC must be tied Low when using COUNT.

DELAY_TYPE

FIXED

VAR_LOAD

VARIABLE

FIXED

String

Delay mode of the input delay line. For further information, see Native Input Delay Type Usage.

DELAY_VALUE

0–1250 (TIME UltraScale)

0–1100 (TIME UltraScale+)

0–511 (COUNT)

0

Decimal

Note:   For BISC to properly align, set OUTPUT_PHASE_90 = FALSE.

TIME mode: Desired value in ps.

UltraScale devices support delays up to 1.25 ns.

UltraScale+ devices support delays up to 1.1 ns.

COUNT mode: Desired value in taps.

DELAY_FORMAT_EXT

TIME(1) or COUNT

TIME

String

DELAY_FORMAT_EXT can be either TIME or COUNT. Must match DELAY_FORMAT.

The attribute value should match DELAY_FORMAT when CASCADE is set to TRUE.

When set to COUNT, the value given in DELAY_VALUE is the number of taps required. EN_VTC_EXT must be tied Low when using COUNT.

DELAY_TYPE_EXT

FIXED

VAR_LOAD

VARIABLE

FIXED

String

Delay mode of the extended delay line. For further information, see Extended Delay Control Signals.

DELAY_VALUE_EXT

0–1250 (TIME UltraScale)

0–1100 (TIME UltraScale+)

0–511 (COUNT)

0

Decimal

Delay value for extended delay.

TIME mode: Desired value in ps.

COUNT mode: Desired value in taps.

For further information, see Extended Delay Control Signals.

REFCLK_FREQUENCY

200.00–2400.00 (UltraScale)

300.00–2666.67 (UltraScale+)

300.0

1 significant digit float

Specification of reference clock frequency in MHz.

This is the frequency of the master clock, PLL_CLK or REFCLK, the BITSLICE_CONTROL uses. This master clock is used by BISC to calibrate any TIME mode delays. The master clock is also used to generate necessary internal clocks for data capturing or data generation. The tap size is not determined by the REFCLK_FREQUENCY. The tap size is defined in the UltraScale device data sheets as TIDELAY_RESOLUTION [Ref 2].

The REFCLK_FREQUENCY attribute is used by the BISC algorithm to calculate the tap size but not affect the tap size.

When the DELAY_FORMAT attribute is set to TIME, the delay equals the value given in the DELAY_VALUE attribute. The delay is specified in ps and is calibrated using the REFCLK_FREQUENCY attribute. The REFCLK_FREQUENCY attribute is used in conjunction with the incoming reference clock to determine the current tap size and therefore how many taps are required to achieve the requested TIME. This calibration, using the reference clock, accounts for the process variation in the device. When the EN_VTC pin is High, the delay is calibrated to provide the TIME across voltage and temperature.

UPDATE_MODE

ASYNC, SYNC, or MANUAL

ASYNC

String

ASYNC: This is the default and preferred use method. Updates to the delay value are independent of the data being received. This mode is the preferred operation mode because it covers the function of both other modes, too.

SYNC: Updates require DATAIN transitions to synchronously update the delay with the DATAIN edges. This mode is suitable for clocks or data that are always available and switches on a periodic basis.

MANUAL: It takes two assertions of LOAD for the new value to take effect. The first LOAD loads the value defined by CNTVALUEIN and the second LOAD must be asserted with an assertion of the CE for the new value to take effect. This is beneficial because you can update the delay when the data becomes idle.

UPDATE_MODE_EXT

ASYNC, SYNC, or MANUAL

ASYNC

String

ASYNC: This is the default and preferred use method. Updates to the delay value are independent of the data being received. This mode is the preferred operation mode because it covers the function of both other modes, too.

SYNC: Updates require DATAIN transitions to synchronously update the delay with the DATAIN edges. This mode is suitable for clocks or data that are always available and switches on a periodic basis.

MANUAL: It takes two assertions of LOAD for the new value to take effect. The first LOAD loads the value defined by CNTVALUEIN and the second LOAD must be asserted with an assertion of the CE for the new value to take effect. This is beneficial because you can update the delay when the data becomes idle. For further information, see Extended Delay Control Signals. Value should match UPDATE_MODE value.

FIFO_SYNC_MODE

TRUE (Reserved) or FALSE

FALSE

BOOLSTRING

FALSE: This attribute defines the relationship between FIFO_WRCLK_OUT and FIFO_RD_CLK. Always set this attribute to FALSE.

Note:   FIFO_SYNC_MODE = TRUE. Reserved for later use.

See Clocking in Native Mode in the BITSLICE_CONTROL section for more information on these clocks.

CASCADE

TRUE or FALSE

FALSE

String

TRUE: Enables cascading of input and output delay lines of neighboring RX and TX bit slices. When both delay lines are cascaded, a delay of 2.5 ns can be realized. The extended delay is controlled by the _EXT pins.

Consider the use of the attributes for the cascaded output delay line in addition to the master input delay attributes.

FALSE: Disables cascading and the extended (_EXT) attributes can be ignored (pull input Low and leave outputs open).

See the Extended Delay Control Signals description for more information on delay cascading with the RX_BITSLICE.

Note:   CASCADE = TRUE has reduced performance and should not be used when performance is critical.

IS_CLK_INVERTED

1'b0 or 1'b1

1'b0

Binary

Similar to the IS_RST_INVERTED attribute but on the RX_CLK path. When IS_CLK_INVERTED = 1 the inverter is used.

When 1, reverses polarity (inverts) the CLK signal.

When 0, the inverter is not used.

IS_RST_DLY _INVERTED

1'b0 or 1'b1

1'b0

Binary

Similar to the IS_RST_INVERTED attribute but on the RST_DLY path. When IS_RST_DLY_INVERTED = 1 the inverter is used.

When 1, reverses polarity (inverts) the RST_DLY signal.

When 0, the inverter is not used.

IS_RST_INVERTED

1'b0 or 1'b1

1'b0

Binary

A selectable local inverter on the reset path that can change the polarity of the reset input. When IS_RST_INVERTED = 1, the inverter is used.

When 1, reverses polarity (inverts) the RST signal.

When 0, the inverter is not used.

SIM_DEVICE

 

Possible Values: ULTRASCALE, ULTRASCALE_PLUS, ULTRASCALE_PLUS_ES1, ULTRASCALE_PLUS_ES2

ULTRASCALE

String

Sets the device version (ULTRASCALE, ULTRASCALE_PLUS, ULTRASCALE_PLUS_ES1, ULTRASCALE_PLUS_ES2)

Notes:

1.When in TIME mode, calibration affects the availability of bit slices within the nibble. See Bank Overview for more information.