RX_BITSLICE Ports

UltraScale Architecture SelectIO Resources User Guide (UG571)

Document ID
UG571
Release Date
2022-08-31
Revision
1.14 English

Table: RX_BITSLICE Ports lists the RX_BITSLICE ports.

Table 2-24:      RX_BITSLICE Ports

Port

Function(1)

I/O

Synchronous Clock Domain

Description

DATAIN

I/O

RX

Input

Asynchronous

This is the input signal from the IOB. When a differential input buffer is used with a single output (example IBUFDS), the RX_BITSLICE adjacent to the P-side of the differential pair is used. If a differential input buffer with complementary outputs (example IBUFDS_DIFF_OUT) is used, adjacent RX_BITSLICEs for both the P and N inputs are used.

The incoming signal from the IOB can be data, clock, or strobe, selected by the DATA_TYPE attribute on the RX_BITSLICE.

When configured as either a clock or both clock and data, DATAIN is the incoming strobe/clock being forwarded through the RX_BITSLICE and to the BITSLICE_CONTROL to create the clock to the other RX_BITSLICEs to capture data. This strobe/clock bit slice must be positioned on a QBC or DBC IOB site, which is always located at bit slice position zero in a nibble. See Clocking in Native Mode in the BITSLICE_CONTROL section for more information.

When the incoming signal from the IOB is data only, it can be located at any bit slice position in the nibble.

Q[7:0]

RX

FPGA

Output

FIFO_RD_CLK

Deserialized (parallel) output data from the RX FIFO going to the interconnect logic.

If the DATA_WIDTH = 4, Q[3:0] outputs the captured data. Q[7:4] can be left unconnected and Q5 represents the serial data stream arriving at DATAIN.

Note:   For BITSLICE 0 and 6 (upper nibble BITSLICE 0), the route through from DATAIN to Q5 can only be used after DLY_RDY is asserted.

If DATA_WIDTH = 8, Q[7:0] represent 8 bits of captured serial data.

RST

RX

FPGA

Input

Asynchronous

Resets the RX_BITSLICE 0 logic, asynchronous assertion, synchronous deassertion, and is active-High. Q resets to zero while RST is asserted.

See Native Mode Bring-up and Reset section for more information.

CLK

RX

FPGA

Input

Asynchronous

Delay line clock used to control LOAD, CE, and INC. All control inputs to delay line element (LOAD, CE, and INC) are synchronous to the clock input (CLK). A clock must be connected to this port when the delay is configured in VARIABLE or VAR_LOAD. CLK can be locally inverted and must be supplied by a global clock buffer.

CE

RX

FPGA

Input

CLK

Clock enable for the delay line register clock.

Note:   Delays might take up to three clock cycles (CLK) to be applied. During this time, input data should not change to ensure output data does not glitch.

RST_DLY

RX

FPGA

Input

Asynchronous (synchronous deassertion to CLK)

Reset port for the delay line within the receiver logic. Resets the internal delay line to the value defined in DELAY_VALUE.

INC

RX

FPGA

Input

CLK

The increment/decrement is controlled by the enable signal (CE). This interface is only available when the delay line is in VARIABLE or VAR_LOAD mode. As long as CE remains High, the delay line is incremented or decremented by one tap every clock (CLK) cycle. The state of INC determines whether the delay line is incremented or decremented: INC = 1 increments; INC = 0 decrements, synchronously to the clock (CLK). If CE is Low, the delay through the delay line does not change (regardless of the state of INC).

When CE goes Low, the increment/decrement operation ceases on the next positive clock edge.

The programmable delay taps in the delay line primitive wrap around. When the last tap delay is reached (CNTVALUEOUT = 511), a subsequent increment function returns to tap 0. The same applies to the decrement function: decrementing from zero moves to tap 511.

LOAD

RX

FPGA

Input

CLK

When in VAR_LOAD mode and UPDATE_MODE = ASYNC, the delay line load port, LOAD, loads the value set by the CNTVALUEIN into the delay line. The value present at CNTVALUEIN[8:0] is the new tap value. The LOAD signal is an active-High signal and is synchronous to the input clock signal (CLK). Wait at least one clock cycle after applying a new value on the CNTVALUEIN bus before applying the LOAD signal. The CE must be held Low during LOAD operation.

Note:   Delays might take up to three clock cycles (CLK) to be applied. During this time, input data should not change to ensure output data does not glitch.

EN_VTC

RX

FPGA

Input

Asynchronous

Enable Voltage, temperature, and process calibration/compensation.

High: Allows BITSLICE_CONTROL to keep delay constant over VT. BITSLICE_CONTROL.EN_VTC must be High for VT compensation to be enabled.

Low: VT compensation is disabled.

When TIME mode is used, the EN_VTC signal must be pulled High during initial BISC.

When COUNT mode is used, the EN_VTC signal must be pulled Low.

When bit slices are used in both TIME and COUNT mode in a nibble, EN_VTC must be pulled High for the bit slices used in TIME mode, and pulled Low for those used in COUNT mode.

CNTVALUEIN[8:0]

RX

FPGA

Input

CLK

The CNTVALUEIN bus is used to dynamically change the loadable tap value. The 9-bit value at the CNTVALUEIN is the number of taps required. New CNTVALUEIN values should only be applied when EN_VTC is Low.

The new value is best applied one clock cycle before applying the LOAD signal. The delay line can be changed from 1 to 8 taps at a time.

For RX_BITSLICEs used as clock/strobe, CNTVALUEIN is not supported.

Clocking in Native Mode in the BITSLICE_CONTROL section describes how the strobe/clock is tuned using BISC. Provide CNTVALUEIN one clock cycle before LOAD pulse High.

CNTVALUEOUT[8:0]

RX

FPGA

Output

CLK

The CNTVALUEOUT pins are used for reporting the current tap value, and read out the amount of taps in the current delay. When EN_VTC is High, CNTVALUEOUT is updated by the BITSLICE_CONTROL.

FIFO_RD_CLK

RX

FPGA

Input

Asynchronous

The deserialized received data is read from the FIFO using the FIFO_RD_CLK signal. The FIFO_RD_CLK signal must be a divided version of the sampling frequency of the incoming data. See FIFO Function in RXTX_BITSLICE.

FIFO_RD_EN

RX

FPGA

Input

FIFO_RD_CLK

Enables a read operation from the FIFO when High. When Low, the FIFO read pointer is held at the same position. The effect of this is that the Q-output shows new data every eight clock cycles assuming write is happening continuously on every clock.

FIFO_EMPTY

RX

FPGA

Output

FIFO_RD_CLK

FIFO empty flag for this bit. This is asserted High when FIFO write and read pointers are the same.

When inverted and registered, connect FIFO_EMPTY to the FIFO_RD_EN to obtain a continuous data stream from the FIFO.

FIFO_WRCLK_OUT

RX

FPGA

Output

PLL_CLK

(for SERIAL_MODE)

or DQS_IN (for source synchronous interfaces)

(BITSLICE_CONTROL)

This signal is only valid for a bit slice positioned at BITSLICE 0 of a nibble. These pins for bit slices in other positions have no routing in the FPGA.

The FIFO_WRCLK_OUT is a copy of the bit slice internal FIFO_WR_CLK. It is a divided version of the data sample clock/strobe. This clock writes the deserialized parallel data in the bit slice into the FIFO.

The use of this port is only recommended for experienced designers.

Additional timing constraints are described in FIFO Function.

CLK_EXT

TX

FPGA

Input

Asynchronous

When CASCADE=TRUE, CLK_EXT and CLK must be connected to the same clock source. Delay line clock used to sample LOAD_EXT, CE_EXT, and INC_EXT. All control inputs to the output delay line element are synchronous to the clock input (CLK_EXT). A clock must be connected to this port when the delay is configured in VARIABLE or VAR_LOAD. The CLK_EXT can be locally inverted, and must be supplied by a global clock buffer.

CE_EXT

TX

FPGA

Input

CLK_EXT

Clock enable for the cascaded output delay line register clock.

RST_DLY_EXT

TX

FPGA

Input

Asynchronous (synchronous deassertion to CLK)

Reset port for the cascaded output delay line. Resets the internal delay line to the value defined in the DELAY_VALUE attribute.

INC_EXT

TX

FPGA

Input

CLK_EXT

The increment/decrement is controlled by the enable signal (CE_EXT). This interface is only available when the delay line is in VARIABLE or VAR_LOAD mode. As long as CE_EXT remains High, the delay line is incremented or decremented by one tap every clock (CLK_EXT) cycle. The state of INC_EXT determines whether the delay line is incremented or decremented: INC_EXT = 1 increments; INC_EXT = 0 decrements, synchronously to the clock (CLK_EXT). If CE_EXT is Low, the delay through the delay line does not change (regardless of the state of INC_EXT). When CE_EXT goes High, the increment/decrement operation begins on the next positive clock edge. When CE_EXT goes Low, the increment/decrement operation ceases on the next positive clock edge.

The programmable delay taps in the delay line primitive wrap around. When the last tap delay is reached (CNTVALUEOUT_EXT = 511), a subsequent increment function returns to tap 0. The same applies to the decrement function: decrementing from zero moves to tap 511.

LOAD_EXT

TX

FPGA

Input

CLK_EXT

When in VAR_LOAD mode, this input loads the value set by the CNTVALUEIN_EXT into the delay line. The value present at CNTVALUEIN_EXT [8:0] is the new tap value. The LOAD_EXT signal is an active-High signal and is synchronous to the input clock signal (CLK_EXT). Wait at least one CLK_EXT clock cycle after applying a new value on the CNTVALUEIN_EXT bus before applying the LOAD_EXT signal. The CE_EXT must be held Low during LOAD_EXT operation.

EN_VTC_EXT

TX

FPGA

Input

Asynchronous

Enable voltage, temperature, and process compensation.

High: Allows BITSLICE_CONTROL to keep delay constant over VT. BITSLICE_CONTROL.EN_VTC must be High for VT compensation to be enabled.

Low: VT compensation is disabled.

When TIME mode is used, the EN_VTC_EXT signal must be pulled High during initial BISC.

When COUNT mode is used, the EN_VTC_EXT signal must be pulled Low.

When bit slices are used in both COUNT and TIME mode in a nibble, EN_VTC_EXT must be pulled High for the bit slices used in TIME mode, and pulled Low for those used in COUNT mode.

CNTVALUEIN_EXT[8:0]

TX

FPGA

Input

CLK_EXT

The CNTVALUEIN_EXT bus is used for dynamically changing the loadable tap value. The 9-bit value at the CNTVALUEIN_EXT bus is the new tap value the output delay line is set to after LOAD_EXT. Provide the value on this bus at least one clock cycle before LOAD_EXT. The delay line can be changed from 1 to 8 taps at a time.

CNTVALUEOUT_EXT[8:0]

TX

FPGA

Output

CLK_EXT

The CNTVALUEOUT_EXT pins are used for reporting the current output delay tap value, and reads out the amount of taps in the current delay. When EN_VTC_EXT is High, CNTVALUEOUT_EXT is updated by the BITSLICE_CONTROL.

The following RX/TX_BIT_CTRL_OUT and RX/TX_BIT_CTRL_IN pins are 40-bit bus connections between the RXTX_BITSLICE (RX_BITSLICE and/or TX_BITSLICE) and the BITSLICE_CONTROL. Each of these 40-bit buses carry data, clocks, RIU, and status signals between the RXTX_BITSLICE (RX_BITSLICE, TX_BITSLICE), TX_BITSLICE_TRI, and BITSLICE_CONTROL, and vice versa.

When a bit slice is used, these buses must be connected to the appropriate BITSLICE_CONTROL input and output bus.

Example:

When RXTX_BITSLICE_2 is used, RX/TX_BIT_CTRL_OUT of that RXTX_BITSLICE must connect to the BITSLICE_CONTROL RX/TX_BIT_CTRL_IN2 and the RX/TX_BIT_CTRL_IN of the RXTX_BITSLICE buses must connect to the BITSLICE_CONTROL RX/TX_BIT_CTRL_OUT2 buses.

These buses are made of dedicated routing between the BITSLICE_CONTROL and bit slices and cannot be accessed or used by logic. It's also not possible to connect an ILA or VIO to these buses, and viewing the buses in simulation is meaningless because the content and bit names of the buses is not disclosed.

RX_BIT_CTRL_IN[39:0]

 

Input

N/A

Input bus from BITSLICE_CONTROL

RX_BIT_CTRL_OUT[39:0]

 

Output

N/A

Output bus to BITSLICE_CONTROL

TX_BIT_CTRL_IN[39:0]

 

Input

N/A

Input bus from BITSLICE_CONTROL

TX_BIT_CTRL_OUT[39:0]

 

Output

N/A

Output bus to BITSLICE_CONTROL

Notes:

1.I/O RX: Connections between the RX_BITSLICE side of the RXTX_BITSLICE and the I/O buffers.
I/O TX: Connections between the TX_BITSLICE side of the RXTX_BITSLICE and the I/O buffers.
RX FPGA: Connections from/to the RX_BITSLICE side of the RXTX_BITSLICE and the logic.
TX FPGA: Connections from/to the TX_BITSLICE side of the RXTX_BITSLICE and the logic.