Receive Clocking

UltraScale Architecture SelectIO Resources User Guide (UG571)

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1.14 English

The RXTX_BITSLICE has two distinct clock/strobe sources, initiated by an attribute or RIU register bit to capture data. The attribute or register bit impacts the functioning of the BITSLICE_CONTROL primitive SERIAL_MODE = TRUE/FALSE.

When the attribute SERIAL_MODE is set to TRUE, the received data is captured using the applied master clock (PLL_CLK or REFCLK). This clock is the DDR capture clock normally running at half the data. Logic in the BITSLICE_CONTROL regenerates and divides the master clock to form required clocks in the receiver.

When the attribute SERIAL_MODE is set to FALSE, then the received data is captured using a clock or strobe forwarded with the data. An attribute (INV_RXCLK) can enable an inverter in this receiver clock path. The clock applied to the BITSLICE_CONTROL master clock input is used by the BISC controller for input delay line calibration and must have the same frequency as the received data rate.


As shown in This Figure, this setup that can be used when:

Only the data is received from a connected component.

The received data contains an embedded clock as in SGMII and some other protocols that are normally fed to a GTH or GTY high-speed serial transceiver.

The clock delivered with the data is not a bit clock but a frame or system-synchronous clock.

Figure 2-65:      Data Capture in Serial Mode

X-Ref Target - Figure 2-65


When data is received, a clock is needed to capture that data. In each of the above cases, BITSLICE_CONTROL master clock (PLL_CLK or REFCLK) is used to capture the data.

The PLL has dedicated high speed and low jitter connections to the BITSLICE_CONTROL primitive. When a MMCM is used, clocks are routed over global FPGA clock routing, and clock buffers BUFG or BUFGCE must be inserted in the clock path causing more jitter. Using a PLL allows capturing higher data rates than when using a MMCM.

The PLL used to generate the data-capture clock must be in the same I/O bank as the receiving RXTX_BITSLICEs. In this mode, all inputs of a nibble can be used as data inputs. When the input data is differential, then bit 6 of the upper nibble cannot be used.

The frequency of the clock is equal to a DDR clock that should be used to capture the received data. For example, receiving a data stream of 1 Gb/s requires that the frequency of the master clock is 500 MHz.

A clock generator in the BITSLICE_CONTROL using DATA_WIDTH and DIV_MODE attributes ensures that all necessary clocks for serial-to-parallel conversion of the data are generated.

For example, capturing 8-bit wide data requires DATA_WIDTH to be set to 8 and DIV_MODE to 4. The captured and serial-to-parallel converted data is written into the RX_BITSLICE output FIFO at a rate of the master_clock/4.

The FIFO_WRCLK_OUT pin of BITSLICE_0 in each nibble provides a copy of the clock used to write data, internal to the RXTX_BITSLICE, in the FIFO. This FIFO_WRCLK_OUT or a clock of the same frequency generated from a PLL or MMCM can then be used as FIFO_RD_CLK.


CAUTION!   When a nibble uses the attribute SERIAL_MODE=TRUE, a BITSLICE_0 must be instantiated into the design and the DATA_TYPE must be set to SERIAL. Even when BITSLICE_0 is not used in the design, it must be connected to an I/O buffer or else the Vivado tools error out. For the upper nibble, BITSLICE_0 is the equivalent of BITSLICE_6 for a byte group. See This Figure for an explanation of bitslice numbering within a byte and nibble.


This Figure shows the setup to be used with all kinds of source synchronous interfaces. These interfaces provide data with related clock or strobe. The BITSLICE_0 received clock or strobe is used to capture the received data in the other RX_BITSLICEs of the nibble, byte, or entire I/O bank. The clock supplied to the BITSLICE_CONTROL master clock input is used to calibrate the input delay lines, and its frequency must be equal to the received data rate.

This kind of interface requires connecting the clock or strobe to the BITSLICE_0 of a nibble. These pins are labeled as dedicated byte clock (DBC), as quad byte clock (QBC), or as a dual purpose pin (GC/QBC). The dual purpose GC/QBC clock input allows the received bit clock to be used to capture the data bits in the other bit slices of the nibble, byte, or I/O bank, but can also be used as clock input for the PLL to generate a valid BITSLICE_CONTROL master clock.

While BITSLICE_0 is used as clock input, the other bit slices of the nibble can be used for data capture. A BITSLICE_0 used as clock input can capture the clock as if it is a data pattern. This can be useful for many kinds of control functionality in a design.

Figure 2-66:      Data Capture in Non-Serial Mode

X-Ref Target - Figure 2-66


Only BITSLICE_0 in a nibble can be used as clock/strobe input. When more bit slices than a nibble are used to capture data, inter-nibble and/or inter-byte clocking must be used. By using this technique, clock/strobe can be forwarded to the entire I/O bank. For example, if a connected device delivers 16 data channels with a single clock, this requires multiple nibbles/bytes to capture data while a single BITSLICE_0 must be defined as the input of the forwarded clock. The clock needs inter-nibble and inter-byte clocking to serve all data channels. The supplied data sample clock or strobe is tuned and maintained over voltage and temperature by the BISC controller in the BITSLICE_CONTROL primitive.


TIP:   A used BITSLICE_0 within a nibble or a combinatorial signal connected to the associated I/O pin passing through the BITSLICE_0 is not available to the application in the FPGA until after the DLY_RDY output pin of the BITSLICE_CONTROL or RDY output pin of IDELAYCTRL in the nibble used by the BITSLICE_0 is HIGH. BITSLICE_0 is used for calibration and is only available after calibration has completed. The Vivado tool generates a Critical Warning that can be demoted by using the XDC Constraint:

set_property UNAVAILABLE_DURING_CALIBRATION TRUE [get_ports <port name>]

There is one exception: In an I/O bank, there is one differential QBC/GC pin set or two single-ended QBC/GC pins. Those can be used to carry a clock to a MMCM or PLL while BISC is running and while the possibly connected BITSLICE_0 is unavailable.

The single received clock, in BITSLICE_0, can be used to capture data in the nibble, byte, or entire I/O bank. Assuming a lower and upper nibble are used, and clocking is passed from the lower nibble to the upper nibble, then the BITSLICE_0 of the lower nibble can carry the input/sample clock while the BITSLICE_0 of the upper nibble can be a normal data input.

DATA_WIDTH and DIV_MODE attributes set a clock generator in the BITSLICE_CONTROL to generate all necessary clock divisions for serial-to-parallel conversion and RX_BITSLICE FIFO write operations.

The received clock/strobe is passed through, tuned, and forwarded by the BITSLICE_CONTROL, and is used to capture received data in the other bit slices. The data is parallelized by a divided version (DIV_MODE) of the capture clock and written into the RX_BITSLICE FIFO. The received clock/strobe that is passed through, tuned, and forwarded by the BITSLICE_CONTROL can be used in RX_BITSLICE_0 to capture an image of the clock. This clock data can be used in the general device logic. The image of the clock is presented in a data format to the interconnect logic and can be used for any design-related functionality.

To read data from the FIFO, a clock must be connected to the FIFO_RD_CLK input. This clock should have the same frequency as the data sample clock divided by the DIV_MODE parameter. The FIFO_RD_CLK can be generated by a PLL or a MMCM. The same PLL that is used for the high speed PLL_CLK can be used to generate this FIFO_RD_CLK.

The FIFO_RD_CLK can also be sourced from the FIFO_WRCLK_OUT of a BITSLICE_0 when this bit slice is used as sample clock input. The BITSLICE_0 used with FIFO_WRCLK_OUT must be in the same I/O bank as the clocked FIFOs.

When SELF_CALIBRATE is TRUE, the received clock is tuned in the BITSLICE_CONTROL by the BISC controller to 90 degrees or 0 degrees depending on RX_CLK_PHASE_P and RX_CLK_PHASE_N attribute values. The BISC controller also compensates the data and clock delay mismatches arriving at the RX_BITSLICE input, but it does not compensate for delays outside the general device logic. The BISC controller runs on the applied master clock, PLL_CLK, or REFCLK input of the BITSLICE_CONTROL. Because the master clock has nothing to do with capturing data, its frequency rate should be set to be equal to the received data rate.

As an extra function, BISC can continuously track voltage and temperature variations to maintain the clock and data timing relationship over V and T. When input delay elements are used in the data input path, BISC tracks for voltage and temperature compensation.

One nibble contains 6 (lower) or 7 (upper) bit slices resulting in the following possible amounts of I/Os:

Single-Ended I/Os

Differential I/Os

1 clock input

1 clock input

5 or 6 data inputs

2 data inputs

One byte combines an upper and a lower nibble resulting in the following possible amounts of I/Os:

Single-Ended I/Os

Differential I/Os

1 clock input

1 clock input

12 data inputs

5 data inputs

One I/O bank is equal to a combination of four bytes, resulting in the following possible amounts of I/Os:

Single-Ended I/Os

Differential I/Os

1 clock input

1 clock input

Up to 51 data inputs

Up to 23 data inputs