Receiver Offset Control in HP I/O Banks

UltraScale Architecture SelectIO Resources User Guide (UG571)

Document ID
UG571
Release Date
2022-08-31
Revision
1.14 English

In HP I/O banks, for a subset of I/O standards, the UltraScale architecture provides the option of canceling the inherent offset of the input buffers that occurs due to process variations (up to ±35 mV). This feature can be accessed through IBUFE3, IBUFDSE3, IOBUFE3, and IOBUFDSE3 primitives as shown in This Figure and This Figure. Offset calibration requires building control logic into your interconnect logic design.

Figure 1-14:      Offset Calibration Connections for Single-Ended I/O Standards

X-Ref Target - Figure 1-14

X16072-offset-calib-conns-for-single-ended-io-standards.jpg
Figure 1-15:      Offset Calibration Connections for Differential I/O Standards

X-Ref Target - Figure 1-15

X16073-offset-calib-conns-for-diff-io-standards.jpg

1.The offset cancellation feature is activated for the supported I/O standards when:

a.Offset control attribute OFFSET_CNTRL is set to FABRIC.

b.OSC_EN port is set to 1'b1 (single-ended I/O standards) or 2'b11 (for differential I/O standards).

 

IMPORTANT:   The value of 2'b10 or 2'b01 is illegal when using OSC_EN for differential I/O standards.

2.After the offset cancellation feature is activated, the input to the buffer is pulled-up to VREF (in differential I/Os, both legs are pulled-up to VREF). Based on the inherent offset of the buffer, the output (O) is either a logic 1 or 0. A logic 1 suggests a positive offset. A logic 0 suggests a negative offset. In simulation, this hardware behavior can be mimicked by setting the simulation-only attribute SIM_INPUT_BUFFER_OFFSET to a negative or positive value from –50 mV to +50 mV. This simulation-only attribute is supported with IBUFE3, IBUFDSE3, IOBUFE3, and IOBUFDSE3 primitives.

3.Based on the value of O, the FABRIC calibration logic should sweep OSC[3:0] in the positive or negative direction until O is seen to flip. The value where O flips is the required offset to cancel the inherent offset of the buffer. Table: Approximate Amount of Offset Cancellation for Each Setting of OSC  shows the approximate amount of offset cancellation provided by each setting of OSC.

Table 1-9:      Approximate Amount of Offset Cancellation for Each Setting of OSC 

OSC[3:0]

Estimated Offset Cancellation (mV)

 

OSC[3:0]

Estimated Offset Cancellation (mV)

0000

0

 

1000

0

0001

–5

 

1001

5

0010

–10

 

1010

10

0011

–15

 

1011

15

0100

–20

 

1100

20

0101

–25

 

1101

25

0110

–30

 

1110

30

0111

–35

 

1111

35

For example, if the buffer input offset is 15 mV, setting OSC[3:0] = 1011 cancels the offset. If the buffer input offset is –10 mV, setting OSC[3:0] = 0010 cancels the offset.

4.If O does not flip, even at the maximum possible offset (–35mV or 35mV), OSC should be set to the maximum –35mV (0111) if O stays at a logic 1 throughout, or +35mV (1111) if O stays at a logic 0 throughout and continue to step 5.

5.After the required offset is determined, OSC_EN should be turned off by setting it to 1'b0 (single ended I/O standards) or 2'b00 (differential I/O standards) and normal operation can resume.

 

RECOMMENDED:   Offset calibration should not be attempted on inputs with external bias or termination.

 

IMPORTANT:   OSC[3:0] is a shared bus among all the I/Os within a half bank (26 consecutive I/Os in the top half or bottom half of a bank).

The I/O standards that support receiver offset control are shown in Table: I/O Standards Supporting Receiver Offset Control .

Table 1-10:      I/O Standards Supporting Receiver Offset Control 

POD12

DIFF_POD12

POD12_DCI

DIFF_POD12_DCI