As shown in This Figure, the setup of a receiver can be divided into the following blocks; an input delay element feeding a set of deserializer registers writing parallelized data in a FIFO and clock generation logic.
The input delay line is always in the signal input path. When an input delay is not wanted, the delay value of the delay should be set to zero. The deserializer registers are divided into three stages, 1:2, 2:4, and 4:8. From here the FIFO input is written. All necessary clocks for the register stages and FIFO write side are generated in the clock generation logic and fed by BITSLICE_CONTROL outputs. The BISC controller in the BITSLICE_CONTROL uses clocks for tuning and aligning the clock to the data. This is discussed in detail in Clocking in Native Mode in the BITSLICE_CONTROL section.
Assume capturing data with the data forwarded clock:
•The forwarded clock must be connected to a BITSLICE_0 of a nibble. These are the QBC or DBC balled inputs.
•The forwarded clock is passed through the BITSLICE_0 into the BITSLICE_CONTROL.
•A clock generator in the BITSLICE_CONTROL creates the necessary clocks to capture and write the data bits into the FIFO.
•The BITSLICE_CONTROL also needs a master or reference clock applied to its PLL_CLK input.
Typically, for low jitter and high performance, this clock is generated by one of the two PLLs in the area behind the I/O bank. The CLKOUTPHY output of the PLL must connect to the BITSLICE_CONTROL.PLL_CLK input without a clock buffer. For source synchronous systems, the frequency of that clock is equal to the bit rate of the captured data.
•Data is captured by a deserializer using the received forwarded clock and writes the deserialized data into the FIFO.
•The clock used to write data into the FIFO is made available to the FPGA logic as FIFO_WRCLK_OUT. Although each RXTX_BITSLICE has a FIFO_WRCLK_OUT pin, the signal is only available at BITSLICE_0 of a nibble.
•The FIFO_WRCLK_OUT can be used instead of a PLL or MMCM as a clock for logic designed in the FPGA and as a read clock for the FIFO. To do this, the FIFO_WRCLK_OUT is passed through a BUFG clock buffer.
Data is written into the FIFO at each rising edge of the internal FIFO write clock, reflected as FIFO_WRCLK_OUT to the FPGA logic. The FIFO write pointer runs from 0 to 7 and then loops around, filling the FIFO with new data.
Here are conditions to read the captured and deserialized data from the FIFO:
•To read data from the FIFO, it needs a read clock (FIFO_RD_CLK). This clock must have the same frequency as the FIFO_WRCLK_OUT clock, and phase unknown (mesochronous). If needed or wanted, the FIFO_WRCLK_OUT can thus be used as FIFO_RD_CLK.
•A second condition to read data from the FIFO is that the FIFO_RD_EN input is High.
Note: When FIFO_RD_EN is kept Low, the read pointer is stopped. Assuming the write clock continues, the write pointer continues to increment, resulting in the FIFO_EMPTY—typically matching every eight FIFO_WRCLK_OUT clock cycles. The eight-cycle behavior is typically observed but is not guaranteed. FIFO_RD_EN circuitry should use the first deassertion of FIFO_EMPTY.
•When the FIFO write and read pointer are equal, meaning that write and read access the same position in the FIFO, a FIFO_EMPTY pulse is generated. This pulse is synchronized with the FIFO_RD_CLK, and it takes two FIFO_RD_CLK cycles before the status is presented at the FIFO_EMPTY pin of the RXTX_BITSLICE.
An example of legal operation of the FIFO in the RXTX_BITSLICE is as follows:
1.Apply a FIFO_RD_CLK to the FIFO.
2.Use the registered version of inverted FIFO_EMPTY signal (operated by the FIFO_RD_CLK).
3.Use this output to enable the FIFO by way of the FIFO_RD_EN input.
The following approach ensures that after the first data is written into the FIFO, it is read and FIFO read pointers never cause the FIFO to generate an empty status signal:
1.At the start, the write and read pointers are zero.
3.The read pointer is stuck because the FIFO is disabled.
4.After the first data write, a non-empty situation is generated.
5.That status is only available to the application after two read clock cycles. This means that write runs two clock cycles ahead of read.
6.FIFO_EMPTY is used through a register, operated on the FIFO_RD_CLK, to enable the FIFO requiring an extra FIFO_RD_CLK cycle. Thus write runs three clock cycles ahead of read.
7.FIFO_EMPTY does not show empty as long as data is written and read from the FIFO.
Two use cases apply:
°Do not touch the FIFO_RD_EN. It is only controlled by the FIFO_EMPTY signal.
°When data from the FIFO needs to be ignored by the application, disable a capture register in the application.
To re-enable the FIFO, wait for FIFO_EMPTY to pulse (Low-High-Low) before applying FIFO_RD_EN. This follows the sequence of the numbered list starting at step 2.