Register Definitions and Addresses

UltraScale Architecture SelectIO Resources User Guide (UG571)

Document ID
UG571
Release Date
2022-08-31
Revision
1.14 English

The following tables provide additional details for the RIU register definitions. Many of the settings are used for memory applications (MIG) and are provided for completeness. For information on how the Memory IP uses the RIU registers, see UltraScale Architecture-Based FPGAs Memory IP LogiCORE IP Product Guide (PG150) [Ref 13].

Table: Register Bit Description (NIBBLE_CTRL0) through Table: Register Bit Description (DFD_CTRL) list register bit descriptions.

Table 2-39:      Register Bit Description (NIBBLE_CTRL0)

NIBBLE_CTRL0

ADDR: 0x00

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Default

 

 

 

 

0

0

0

0

 

0

0

0

0

0

1

1

Access

 

 

 

 

R/W

R/W

R

R/W

 

R/W

R/W

R/W

R/W

R/W

R/W

R/W

15:12

Reserved

11

DIS_DYN_MODE_RX: Disable gate delay dynamic mode (MIG) or enable receive delay line updates using RIU. See UltraScale Architecture-Based FPGAs Memory IP LogiCORE IP Product Guide (PG150) for details [Ref 13].

10

DIS_DYN_MODE_TX: Disable output delay dynamic mode (MIG) or enable transmit delay lines updates using RIU.

9

GT_STATUS: Monitor gate placement relative to strobe/clock.

8

CLR_GATE: Used for strobe/clock gate training. Resets the gating logic.

7

Reserved

6

RXGATE_EXTEND: Enable preamble extension for DQS_BIAS.

5

RX_GATE: Enable receive strobe/clock gating.

4

TX_GATE: Enable transmit clock gating.

3

SERIAL_MODE: Set to 1 to enable PLL_CLK as a sample clock. This mode is used for data sampling of a serial bitstream such as SGMI.

BISC manipulates this bit during initial BISC calibration. So if SERIAL_MODE is selected using the RIU register bit instead of the attribute setting, you must set this bit again after DLY_RDY assertion of High. Otherwise the PHY will not be in serial mode operation.

2

INVERT_RX_CLK: Invert the clock path from IOB to RX_BITSLICE. This is for clock path through read DQS_IN.

1

EN_NDQS:
Set to 1 to pass a source-synchronous clock NCLK_NIBBLE_OUT from the other nibble's DQS gating circuit through NQTR slave delay.
Set to 0 to pass a clock from the present nibble's DQS gating circuit through the NQTR slave delay.

0

EN_PDQS:
Set to 1 to pass a source-synchronous clock PCLK_NIBBLE_OUT from the other nibble's DQS gating circuit through PQTR slave delay.
Set to 0 to pass a clock from the present nibble's DQS gating circuit through the PQTR slave delay.

Table 2-40:      Register Bit Description (NIBBLE_CTRL1)

NIBBLE_CTRL1

ADDR: 0x01

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Default

 

 

 

 

0

0

0

0

0

0

0

0

0

0

1

1

Access

 

 

 

 

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

15:12

Reserved

11:2

TX_DATA_PHASE: When set, shifts the output data by 90 degrees.

[11]: Master data bit slice

[10]: Master clock bit slice

[9]: 3-state bit slice

[8:2]: TX_BITSLICEs

1

RX_CLK_PHASE_N: When set, shifts any input clock or strobe after entering the bit slice from the I/O by 90 degrees. Leaving this bit at 0 maintains a 0 degrees phase shift clock/strobe.

0

RX_CLK_PHASE_P: When set, shifts any input clock or strobe after entering the bit slice from the I/O by 90 degrees. Leaving this bit at 0 maintains a 0 degrees phase shift clock/strobe.

Table 2-41:      Register Bit Description (CALIB_CTRL)

CALIB_CTRL

ADDR: 0x02

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Default

0

0

0

0

0

0

1

1

1

1

1

1

1

1

1

1

Access

R

R/W

R/W

R

R

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

15

PAUSE_RDY: VT tracking state machine pause indication.

14

DIS_VTTRACK_QTR: Enable or disable auto VT tracking for the slave PQTR/NQTR delays.

13

BSC_RESET: Software reset for BISC.

12

PHY_RDY: PHY calibration complete status. This is the RIU equivalent of the VTC_RDY signal.

11

FIXDLY_RDY: Fixed delay calibration complete status. This is the RIU equivalent of the DLY_RDY signal.

3:10

CALIBRATE_EN: Inject the reference clock/PLL CLK into per-bit datapaths for the receive channels to perform self-calibration.

CALIBRATE_EN[6:0]: Per RX_BITSLICE.

CALIBRATE_EN(7): Master.

2

DIS_VTTRACK_OBIT: Enable or disable auto VT tracking for all output delay lines.

1

DIS_VTTRACK_IBIT: Enable or disable auto VT tacking for all input delay lines.

0

CALIBRATE: Turn self-calibration on or off.

Table 2-42:      Register Bit Description (BS_CTRL)

BS_CTRL

ADDR: 0x05

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Default

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

Access

R

R/W

R/W

R

R

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

15:9

IFIFO_BYPASS: Bypass the FIFO of the selected bit slice and pass data directly to the interconnect logic. (1 = bypass, 0 = use FIFO). No longer supported.

8

MON_RESET: Reset the monitor DLL (active-High).

7

BS_RESET_TRI: Reset the 3-state bit slice (active-High). If TX_OUTPUT_PHASE_90 is used, TBYTE_IN must be 0x0 when BS_RESET is being performed.

6:0

BS_RESET: Reset the selected bit slice(s) (active-High). If TX_OUTPUT_PHASE_90 is used, TBYTE_IN must be 0x0 when BS_RESET is being performed.

Table 2-43:      Register Bit Description (IODELAY_INC_BCAST_CTRL)

IODELAY_INC_BCAST_CTRL

ADDR: 0x06

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Default

 

 

 

 

 

 

0

0

0

0

0

0

0

0

0

0

Access

 

 

 

 

 

 

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

15

Reserved

9

BCAST_SEL: Broadcast input or output delay lines (1 = input delay, 0 = output delay).

8

BCAST_INC: Broadcast INC or DEC (1 = INC, 0 = DEC).

7

BCAST_EN: Broadcast enable of fine delay adjustment to delay line [0:6] (1 = enable, 0 = disable).

6:0

BCAST_MASK_IDLY[0:6]: Disable broadcast of INC/DEC to selected delay line (1 = disable, 0 = enable).

Note:   BISC continuously increments and/or decrements the delay during self-calibration so be careful before writing to input delay lines.

Table 2-44:      Register Bit Description (PQTR)

PQTR

ADDR: 0x07

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Default

 

 

 

 

 

 

 

0

0

0

0

0

0

0

1

1

Access

 

 

 

 

 

 

 

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

15

INC: Increment. See Table: RIU Delay Adjustments (PQTR, NQTR, MON).

14

DEC: Decrement. See Table: RIU Delay Adjustments (PQTR, NQTR, MON).

13

CRSE: See Table: RIU Delay Adjustments (PQTR, NQTR, MON). Coarse delay increment or decrement of 8 taps. Might cause capture clock to glitch when used for PQTR adjustments. Issue a BS_RESET (ADDR=0x05) to fix alignment after any coarse jump.

12:9

Reserved

8:0

PQTR: P-side quarter delay of 0 to 511 taps.

Table 2-45:      Register Bit Description (NQTR)

NQTR

ADDR: 0x08

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Default

0

0

0

 

 

 

 

0

0

0

0

0

0

0

1

1

Access

W

W

W

 

 

 

 

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

15

INC: Increment. See Table: RIU Delay Adjustments (PQTR, NQTR, MON).

14

DEC: Decrement. See Table: RIU Delay Adjustments (PQTR, NQTR, MON).

13

CRSE: See Table: RIU Delay Adjustments (PQTR, NQTR, MON). Coarse delay increment or decrement of 8 taps. Might cause capture clock to glitch when used for PQTR adjustments. Issue a BS_RESET (ADDR = 0x05) to fix alignment after any coarse jump.

12:9

Reserved

8:0

NQTR: N-side quarter delay of 0 to 511 taps.

Table 2-46:      Register Bit Description (MON)

MON

ADDR: 0x09

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Default

0

0

0

 

 

 

0

0

0

0

0

0

0

0

0

0

Access

W

W

W

 

 

 

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

15

INC: Increment. See Table: RIU Delay Adjustments (PQTR, NQTR, MON).

14

DEC: Decrement. See Table: RIU Delay Adjustments (PQTR, NQTR, MON).

13

CRSE: See Table: RIU Delay Adjustments (PQTR, NQTR, MON).

12:10

Reserved

9:0

MON: Monitor delay of 0 to 1023 taps.

Table 2-47:      RIU Delay Adjustments (PQTR, NQTR, MON)

INC

DEC

CRSE

RIU Action

0

0

X

Load RIU_WR_DATA[8:0] into delay.

1

1

X

Load RIU_WR_DATA[8:0] into delay.

0

1

0

Decrement delay by 1 tap.

0

1

1

Decrement delay by 8 taps.

1

0

0

Increment delay by 1 tap.

1

0

1

Increment delay by 8 taps.

Table 2-48:      Register Bit Description (ODELAYxx)

ODELAYxx

ADDR: 0x0A–0x11(1)

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Default

0

0

 

 

 

 

 

0

0

0

0

0

0

0

0

0

Access

W

W

 

 

 

 

 

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

15

INC: Increment delay. See Table: RIU Delay Adjustments (IDELAY, ODELAY).

14

DEC: Decrement delay. See Table: RIU Delay Adjustments (IDELAY, ODELAY).

13:9

Reserved

8:0

Output delay line: Tap value between 0 and 511. Fine delay adjustment of write data bits. Can be used for per-bit deskew or DDR write leveling.

Notes:

1.ADDR: 0x0A is the output delay in the TX_BITSLICE_TRI of the nibble. ADDR: 0X0B to 0x11 are the output delays in the TX_BITSLICEs of the nibble.

Table 2-49:      Register Bit Description (IDELAYxx)

IDELAYxx

ADDR: 0x12–0x18

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Default

0

0

 

0

0

0

0

0

0

0

0

0

0

0

0

0

Access

W

W

 

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

15

INC: Increment delay. See Table: RIU Delay Adjustments (IDELAY, ODELAY).

14

DEC: Decrement delay. See Table: RIU Delay Adjustments (IDELAY, ODELAY).

13

Reserved

12:9

RX_DCC: Input delay line duty cycle correction.

8:0

Input delay line: Tap value between 0 and 511. Fine delay adjustment of read data bits. Can be used for per-bit deskew and placement of each data bit relative to the sample clock.

Table 2-50:      RIU Delay Adjustments (IDELAY, ODELAY)

INC

DEC

RIU Action

0

0

Load RIU_WR_DATA[8:0] into delay.

0

1

Decrement delay by 1 tap.

1

0

Increment delay by 1 tap.

1

1

Load RIU_WR_DATA[8:0] into delay.

Table 2-51:      Register Bit Description (PQTR_ALIGN, NQTR_ALIGN, MON_ALIGN, IODELAY_ALIGN)

*_ALIGN

ADDR: 0x19–0x22

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Default

 

 

 

 

 

 

 

 

 

0

0

0

0

0

0

0

Access

 

 

 

 

 

 

 

 

 

R/W

R/W

R/W

R/W

R/W

R/W

R/W

17:7

 

6:0

_ALIGN: Stores the align value after calibration. During initial calibration (when SELF_CALIBRATE is set to ENABLE), BISC programs this register to match the data delay to the sample clock/strobe delay.

Table 2-52:      Register Bit Description (PQTR_RATIO, NQTR_RATIO, IODELAY_RATIO)

*_RATIO

ADDR: 0x23–0x2B

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Default

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

Access

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

15:0

_RATIO: Stores the ratio value after calibration. Used by BISC when EN_VTC of BISTSLICE_CONTROL is asserted High. BISC calculates the baseline for Voltage and Temperature compensation.

Table 2-53:      Register Bit Description (WL_DLY_RNK)

WL_DLY_RNK

ADDR: 0x2C–0x2F

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Default

 

 

0

0

0

0

0

0

0

0

0

0

0

0

0

0

Access

 

 

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

15:14

Reserved

13

WL_TRAIN: Set to 1 to put bit slices into write leveling mode. 3-states the data bits while allowing the strobe/clock bits to drive the output buffers. This bit is only present at address 0x2C and does not exist for 0x2D, 0x2E, and 0x2F registers.

12:9

WL_DLY_CRSE: Coarse delay adjustment of 1/2 PLL_CLK period on write data/strobe/clock versus clock.

8:0

WL_DLY_FINE: Fine delay adjustment on write data/strobe/clock versus clock.

Table 2-54:      Register Bit Description (RL_DLY_RNK)(2)

RL_DLY_RNK

ADDR: 0x30–0x33

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Default

 

 

 

0

0

0

0

0

0

0

0

0

0

0

0

0

Access

 

 

 

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

15:13

Reserved

12:9

RL_DLY_CRSE: Coarse delay adjustment of 1/2 PLL_CLK period on read strobe/clock gate.

8:0

RL_DLY_FINE: Fine delay adjustment on read strobe/clock gate.

Notes:

2.Reserved for memory interface generator (MIG). For memory designs using the RL_DLY_RNK, the PLL clock source (CLKIN for the PLL connected to BITSLICE_CONTROL) and RIU_CLK (BITSLICE_CONTROL) must be sourced from the same MMCM with the same phase shift to ensure asynchronous transfers are not corrupted.

Table 2-55:      Register Bit Description (RD_IDLE_COUNT)

RD_IDLE_COUNT

ADDR: 0x34

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Default

 

 

 

 

 

 

 

 

 

 

0

0

0

0

0

0

Access

 

 

 

 

 

 

 

 

 

 

R/W

R/W

R/W

R/W

R/W

R/W

15:6

Reserved

5:0

Number of clocks (frequency of PLL_CLK/DATA_WIDTH) after PHY_RDEN deassertion and before turning off ODT termination in IOB.

Table 2-56:      Register Bit Description (RL_DLY_RATIO)

RL_DLY_RATIO

ADDR: 0x35

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Default

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

Access

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

15:0

RL_DLY_RATIO: This stores the RATIO value after calibration. Used by BISC for strobe/clock gating and VT tracking.

Table 2-57:      Register Bit Description (RL_DLY_QTR)

RL_DLY_QTR

ADDR: 0x36

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Default

 

 

 

 

 

 

 

0

0

0

0

0

0

0

0

0

Access

 

 

 

 

 

 

 

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

15:9

Reserved

8:0

RL_DLY_QTR: Set from 0 to 511 taps of fine delay. Determines the 90-degree delay on DQS/clock. Used for DQS gating and VT tracking.

Table 2-58:      Register Bit Description (DBG_WR_STATUS)

DBG_WR_STATUS

ADDR: 0x37

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Default

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

Access

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R

15:0

DBG_WR_STATUS: Debug status for write.

Table 2-59:      Register Bit Description (DBG_RW_INDEX)

DBG_RW_INDEX

ADDR: 0x38

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Default

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

Access

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

15:8

DBG_WR_INDEX: Multiplexer selection address for debug status write.

0x00: No write.

0x01–0x7F: Write status to BISC.

0x80–0xFF: Write status to other modules.

7:0

DBG_RD_INDEX: Multiplexer selection address for debug status read.

0x00–0x7F: Read status from BISC.

0x80–0xFF: Read status from other modules.

Table 2-60:      Register Bit Description (DBG_RD_STATUS)

DBG_RD_STATUS

ADDR: 0x39

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Default

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

Access

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R

15:0

DBG_RD_STATUS: Debug status for read.

Table 2-61:      Register Bit Description (DFD_CTRL)

DFD_CTRL

ADDR: 0x3A

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Default

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0

Access

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

R/W

15:1

Reserved

0

DBG_CT_START_EN: DFD debug counter start.

Notes:

1.There is no address decoding and no registers for addresses ranging from 0x3B to 0x3F.

 

Table 2-62:      RIU Registers and Their Corresponding Attributes

Attribute

Register

Default

Description

Position

Bits

EN_OTHER_PCLK

NIBBLE_CTRL0

FALSE

Set to 1 to pass a source synchronous clock from the other nibble's strobe/clock gating circuit through the PQTR slave delay.

Set to 0 to pass a clock from the present nibble's strobe/clock gating circuit through the PQTR slave delay.

0

EN_PDQS

EN_OTHER_NCLK

NIBBLE_CTRL0

FALSE

Set to 1 to pass a source synchronous clock from the other nibble's strobe/clock gating circuit through the NQTR slave delay.

Set to 0 to pass a clock from the present nibble's strobe/clock gating circuit through the NQTR slave delay.

1

EN_NDQS

INV_RXCLK

NIBBLE_CTRL0

FALSE

Invert clock path from IOB to RX_BITSLICE.

2

INVERT_RX_CLK

SERIAL_MODE

NIBBLE_CTRL0

FALSE

Set to 1 to put bit slice read paths into SERIAL_MODE. This mode is used for sampling a serial data stream such as SGMII.

If serial mode is selected by setting SERIAL_MODE=1 (NIBBLE_CTRL0, Bit 3), the SERIAL_MODE setting must be reassigned after DLY_RDY = 1. The SERIAL_MODE setting reverts to the programmed settings when DLY_RDY is asserted.

3

SERIAL_MODE

TX_GATING

NIBBLE_CTRL0

FALSE

Disable clock gating in write clock path.

4

TX_GATE

RX_GATING

NIBBLE_CTRL0

FALSE

Disable clock gating in read clock path.

5

RX_GATE

RXGATE_EXTEND

NIBBLE_CTRL0

FALSE

BQS bias enable.

6

RXGATE_EXTEND

RX_CLK_PHASE_P

NIBBLE_CTRL1

SHIFT_0

Apply a phase shift of 90 degrees to the received clock.

0

RX_CLK_PHASE_P

RX_CLK_PHASE_N

NIBBLE_CTRL1

SHIFT_0

Apply a phase shift of 90 degrees to the received clock.

1

RX_CLK_PHASE_N

TX_OUTPUT_PHASE_90

NIBBLE_CTRL1

FALSE

Per transmitter delays output phase by 90 degrees when set to TRUE.

2:11

TX_DATA_PHASE

SELF_CALIBRATE

CALIB_CTRL

ENABLE

Turn self-calibration (BISC) on or off.

0

CALIBRATE

IDLY_VT_TRACK

CALIB_CTRL

TRUE

Enable VT tracking for input delay lines.

1

DIS_VTTRACK_IBIT

ODLY_VT_TRACK

CALIB_CTRL

TRUE

Enable VT racking for output delay lines.

2

DIS_VTTRACK_OBIT