Register Interface Unit (RIU)

UltraScale Architecture SelectIO Resources User Guide (UG571)

Document ID
UG571
Release Date
2022-08-31
Revision
1.14 English

Using the register interface unit (RIU), the BITSLICE_CONTROL primitive can be turned into a processor peripheral block. The RIU interface is a set of 64 read/write, 16-bit registers, acting as a dynamically accessible processor peripheral interface providing full control over every function and feature of a nibble: control of all input, output, 3-state, and all delay lines (input, output and quarter), voltage and temperature (VT) tracking, clocking options, and built-in self-calibration (BISC). The RIU interface is represented in the BITSLICE_CONTROL component as shown in This Figure.

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Figure 2-74:      RIU in the BITSLICE_CONTROL

X-Ref Target - Figure 2-74

X16042-riu-in-the-bitslice_control.jpg

Each nibble has its own BITSLICE_CONTROL and therefore its own RIU interface. Two nibbles can be combined in a byte, so a byte can have two RIU interfaces. To allow easy control of both RIU interfaces in a byte, a RIU_OR primitive exists.

The RIU_OR primitive combines both nibble RIU interfaces of a byte into a single RIU interface. This Figure and Table: RIU_OR Ports  show the RIU_OR primitive and its pins. A possible setup joining two nibble RIU into a byte-wide RIU using the RIU_OR primitive is shown in This Figure. The RIU_NIBBLE_SEL pin of each RIU is used as the MSB address, putting the upper nibble in the upper address space.

Figure 2-75:      RIU Primitive

X-Ref Target - Figure 2-75

X16792-riu-primitive.jpg

 

 

Table 2-36:      RIU_OR Ports 

Port

I/O

Description

RIU_RD_DATA_UPP[15:0]

Input

Connect to RIU_RD_DATA of the upper nibble BITSLICE_CONTROL.

RIU_RD_DATA_LOW[15:0]

Input

Connect to RIU_RD_DATA of the lower nibble BITSLICE_CONTROL.

RIU_RD_VALID_UPP

Input

Connect to RIU_VALID of the upper nibble BITSLICE_CONTROL.

RIU_RD_VALID_LOW

Input

Connect to RIU_VALID of the lower nibble BITSLICE_CONTROL.

RIU_RD_DATA[15:0]

Output

Combined RIU data bus to interconnect logic.

RIU_RD_VALID

Output

Combined RIU read valid signal to interconnect logic.

 

Table 2-37:      RIU_OR Attribute

Attribute

Values

Default

Type

Description

SIM_DEVICE

ULTRASCALE, ULTRASCALE_PLUS, ULTRASCALE_PLUS_ES1, ULTRASCALE_PLUS_ES2

ULTRASCALE

String

Sets the device version

(ULTRASCALE, ULTRASCALE_PLUS, ULTRASCALE_PLUS_ES1, ULTRASCALE_PLUS_ES2)

Figure 2-76:      RIU_OR Combining Two RIU Ports

X-Ref Target - Figure 2-76

X16793-riu_or-combining-two-riu-ports.jpg