Revision History

UltraScale Architecture SelectIO Resources User Guide (UG571)

Document ID
Release Date
1.14 English

The following table shows the revision history for this document.






Chapter 1: Updated note about DQS_BIAS in Table: Allowed Attributes for the LVDS I/O Standards .

Chapter 2: Updated description of ODDR_MODE in Table: OSERDESE3 Attributes. Updated descriptions of CLK, LOAD, and RST in Table: IDELAYE3 Ports and Table: ODELAYE3 Ports. Updated possible values for REFCLK_FREQUENCY in Table: IDELAYE3 Attributes. Added This Figure. Added This Equation. Updated values for REFCLK_FREQUENCY and UPDATE_MODE in Table: ODELAYE3 Attributes. Updated step 6a and step 4a in VAR_LOAD Mode. Added tip about IDELAYCTRLs and BITSLICE_CONTROLs to IDELAYCTRL. Added note to description of RST in Table: IDELAYCTRL Ports  and Table: BITSLICE_CONTROL Ports. Updated step c and added step d to Release Reset. Updated third paragraph with description of designs with multiple nibbles being used within a bank in Mixing Native and Non-Native Mode I/O in a Nibble. Changed all instances of Align_Value to Align_Delay. Added This Equation and This Equation. Updated values of RX_REFCLK_FREQUENCY and TX_REFCLK_FREQUENCY in Table: RXTX_BITSLICE Attributes. Updated values of REFCLK_FREQUENCY in Table: RX_BITSLICE Attributes, Table: TX_BITSLICE Attributes, and Table: TX_BITSLICE_TRI Attributes.

Chapter 3: In Table: Supported Features in the HD I/O Banks, added /SUB_LVDS to 2.5V I/O standards and updated maximum data rate to 250 Mb/s DDR. Updated first paragraph in HD I/O Interface Logic.



Chapter 1: Added description of output-only IOBs to VREF. Updated step 2 in DCI I/O Standard Support. Updated JEDEC specifications in LVCMOS. Added note about changing drive setting to Table: Allowed Attributes for the LVCMOS12 I/O Standard . Updated first paragraph in HSTL_ I_DCI, HSTL_I_DCI_12, and HSTL_ I_DCI_18. Updated This Figure and This Figure. Added description of alternate bias and termination to Receiver Termination.

Chapter 2: Added sentence about SDR input and output registers to Simple Registered Inputs and Outputs. Updated description of SR in Table: ODDRE1 Ports . Updated description of RST in Table: ISERDESE3 Ports and Table: OSERDESE3 Ports . Updated description of ODDR_MODE in Table: OSERDESE3 Attributes. Updated description of CNTVALUEOUT[8:0] in Table: IDELAYE3 Ports. Updated delay line procedures in VAR_LOAD Mode and VAR_LOAD Mode. Updated descriptions of CNTVALUEOUT[8:0] and RST in Table: ODELAYE3 Ports. Added description of RXTX_EN_VTC to first paragraph of FIXED Mode and FIXED Mode. Updated description of RXTX_BITSLICE.EN_VTC port in VARIABLE Mode. In FIFO Function, clarified that flip-flop for FIFO_RD_EN is optional and only required when timing cannot be met. Updated descriptions of RX_CNTVALUEOUT[8:0] and TX_CNTVALUEOUT[8:0] in Table: RXTX_BITSLICE Ports. Updated descriptions of CNTVALUEOUT[8:0] and CNTVALUEOUT_EXT[8:0] in Table: RX_BITSLICE Ports. Updated description of CNTVALUEOUT[8:0] in Table: TX_BITSLICE Ports and Table: TX_BITSLICE_TRI Port Descriptions. Updated description of TBYTE_IN[3:0] in Table: BITSLICE_CONTROL Ports. Updated description of TX_GATING in Table: BITSLICE_CONTROL Attributes. Updated step 5b in Release Reset. Updated description of bits 7 and 6:0 in Table: Register Bit Description (BS_CTRL). Updated description of bit 13 in Table: Register Bit Description (PQTR) and Table: Register Bit Description (NQTR).

Chapter 3: Added POD to list of standards in Internal VREF .



Chapter 1: Updated fifth paragraph in Introduction to the UltraScale Architecture. Updated I/O Tile Overview. Added DQS_BIAS to Table: HSUL Allowed Attributes .

Chapter 2: Added note about delay ratio register to VARIABLE Mode. Added note about VT compensation to TX_CNTVALUEIN[8:0] description in Table: RXTX_BITSLICE Ports. Added note about changing delays using VT compensation to CNTVALUEIN[8:0] description in Table: TX_BITSLICE Ports.

Appendix B: Added Zynq UltraScale+ RFSoC Data Sheet: Overview (DS889) to References.



SelectIO Interface Resources. Updated N and P sides under DQS_BIAS. Added LVDS_PRE_EMPHASIS and EQUALIZATION attributes to Table: Allowed Attributes for the MIPI_DPHY_DCI Standard , and the attributes are explained for Vivado® Design Suite version 2019.1.1.

SelectIO Interface Logic Resources. Added a note to the CE port and to the CE and LOAD ports in Table: IDELAYE3 Ports, Table: ODELAYE3 Ports, Table: RX_BITSLICE Ports, and Table: TX_BITSLICE Ports. Updated Count mode in the TX_DELAY_VALUE attribute of Table: RXTX_BITSLICE Attributes. Updated I/O in This Figure. Updated DQS_BIAS. Updated Receiver Setup. Updated This Figure title.



SelectIO Interface Resources. Updated LVDS and LVDS_25.

SelectIO Interface Logic Resources. Clarified port descriptions for Component Primitives. Removed the IDELAYCTRL reference from the COUNT mode reset sequence on page 174. Under Release Reset, EN_VTC applies to IDELAYs/ODELAYs. Under Native Input Delay Type Usage, clarified that the EN_VTC applies to RXTX_BITSLICE. In Table: RX_BITSLICE Attributes, corrected IS_CLK_INVERTED/IS_RST_DLY_INVERTED attributes. Clarified that the 8 tap restriction is the limit and delays can be changed from 1 to 8 taps.



SelectIO Interface Resources. Updated DQS_BIAS. Starting with Vivado® Design Suite 2018.1, the DQS_BIAS attribute must be set on the port, not on the cell. Added notes that drivers and receivers must be at the same voltage level. Added the last row (OUTPUT_IMPEDANCE) to Table: HSUL Allowed Attributes . Deleted Figure 2-20: COUNT Mode with Fast Updates.

SelectIO Interface Logic Resources. Updated Table: ODDRE1 Attributes . Clarified reserved bits and defaults in Table: Register Bit Description (NIBBLE_CTRL0) through Table: Register Bit Description (DFD_CTRL).

High Density I/O Resources. Added the ZHOLD heading. Updated DDR Outputs (ODDRE1).



In Chapter 2, updated BITSLICE and waveform information. Updated This Figure, This Figure, This Figure, This Figure, and Figure 2-20. Changed RXTX_BITSLICE to ISERDES in This Figure. Added Count mode with fast update information and This Figure. Updated Figure 2-20 and Figure 2-25. Updated This Figure, This Figure, and This Figure. The Values and Description changed in Table: IDELAYCTRL Attribute. The Component Mode Reset Sequence was updated. Added Table: Bidirectional Support by I/O Bank, Bidirectional Support by I/O Bank. Updated Caution on page 306 and Tip on page 307. Updated Caution on page 316. Updated Table: RXTX_BITSLICE Ports for ports RX_RST and FIFO_RD_EN and TX_RST. Updated Table: RXTX_BITSLICE Ports attribute RX_REFCLK_FREQUENCY and TX_REFCLK_FREQUENCY. Updated Table: RX_BITSLICE Ports port RST. Updated Table: TX_BITSLICE Ports port RST. Updated Table: TX_BITSLICE_TRI Port Descriptions port RST. Updated Table: TX_BITSLICE_TRI Attributes attribute REFCLK_FREQUENCY. Updated the REFCLK port and BITSLICE_CONTROL port REFCLK in Table: BITSLICE_CONTROL Ports. Updated the REFCLK_SRC attribute and BITSLICE_CONTROL attribute in Table: BITSLICE_CONTROL Attributes. Updated Table: RIU Ports port RIU_WR_EN. Updated Table: Register Bit Description (NIBBLE_CTRL1), Table: Register Bit Description (DBG_WR_STATUS), and Table: Register Bit Description (DBG_RD_STATUS).



This book was updated for UltraScale™ and UltraScale+™ devices. The SIM_DEVICE attribute was added to several bit slice attribute tables.

Chapter 2: Extensive clarifications were made, including clarifications for BITSLICE_0 restrictions. Updated delay line procedures when multiple updates are required for component primitives and native primitives. For component primitives, updated primitive port descriptions and attributes. For native primitives, updated primitive port descriptions and attributes.

Additionally, added IS_C_INVERTED, IS_CB_INVERTED in Table: IDDRE1 Attributes . Added IS_D1_INVERTED, IS_D2_INVERTED in Table: ODDRE1 Attributes . Added waveforms to describe latencies (This Figure, This Figure). Updated CLK_B description (Table: ISERDESE3 Ports). Added IS_CLK_INVERTED, IS_CLK_B_INVERTED, IS_RST_INVERTED and SIM_DEVICE (Table: ISERDESE3 Attributes). Added OSERDES latency (This Figure). Updated T description in Table: OSERDESE3 Ports . Added IS_CLK_INVERTED, IS_CLKDIV_INVERTED, IS_RST_INVERTED, and SIM_DEVICE (Table: OSERDESE3 Attributes). Updated REFCLK_FREQUENCY requirements for TIME mode in the IDELAYE3 section. Updated descriptions for RST, EN_VTC, DELAY_VALUE, and DELAY_FORMAT (Table: IDELAYE3 Attributes). Added SIM_DEVICE (Table: IDELAYE3 Attributes). Updated delay procedures for updating VARIABLE and VAR_LOAD to describe multiple updates (DELAY_TYPE descriptions in IDELAY, ODELAY, and Native Input Delay Type Usage). Updated descriptions for RST and EN_VTC (Table: ODELAYE3 Ports). Updated DELAY_VALUE for UltraScale+ devices (Table: ODELAYE3 Attributes). Added SIM_DEVICE (Table: ODELAYE3 Attributes). Updated Variable Mode waveform (This Figure) for multiple updates. Added Table: IDELAYCTRL Attribute. Removed DELAY_TYPE=FIXED from Component Mode Reset Sequence. Updated This Figure to show BUFGCE_DIV usage from a single MMCM clock. Added MMCM descriptions for clock outputs and This Figure. Updated REFCLK_FREQUENCY requirements in Mixing Native and Non-Native Mode I/O in a Nibble. Added latency waveforms for RX_BITSLICE (This Figure, This Figure) and TX_BITSLICE (This Figure, This Figure,). Updated This Figure for multiple updates. Updated descriptions and added TX_OUTPUT_PHASE_90 restriction for Table: RXTX_BITSLICE Attributes. Added UltraScale+ device values and added SIM_DEVICE to Table: RXTX_BITSLICE Attributes. Added UltraScale+ device values for Table: RX_BITSLICE Attributes. Added SIM_DEVICE to Table: RX_BITSLICE Attributes. Updated T, TBYTE_IN descriptions for Table: TX_BITSLICE Ports. Added UltraScale+ device values for Table: TX_BITSLICE Attributes. Added TX_OUTPUT_PHASE_90 restriction for Table: TX_BITSLICE Attributes. Added latency figures for TX_BITSLICE_TRI (This Figure, This Figure), Added UltraScale+ device values and TX_OUTPUT_PHASE_90 restriction for Table: TX_BITSLICE_TRI Attributes. Added SIM_DEVICE (Table: TX_BITSLICE_TRI Attributes, Table: BITSLICE_CONTROL Attributes). Highlighted strobe operation during reset sequence should either be held in reset (updated This Figure) or bitslip is required. Added Native Mode Bring-up when using multiple banks and when a bank uses multiple interfaces. Added SIM_DEVICE to Table: RXTX_BITSLICE Attributes. Added RIU Registers 0x37, 0x38, and 0x39 (Table: Register Bit Description (DBG_WR_STATUS),Table: Register Bit Description (DBG_RW_INDEX), and Table: Register Bit Description (DBG_RD_STATUS)).



Chapter 1: Updated DCI—Only Available in the HP I/O Banks. Updated sections in Uncalibrated Input Termination in I/O Banks, IBUF_IBUFDISABLE, IBUF_INTERMDISABLE, IBUFDS_DIFF_OUT_IBUFDISABLE, IBUFDS_DIFF_OUT_INTERMDISABLE and many more.

Chapter 2: This chapter was rewritten for clarification. In the Component Primitives section, replaced IDELAY_CTRL with IDELAYCTRL. Reorganized Native Primitives section and updated sub-sections with many clarifications. Added Synchronous Clock Domain columns to port tables Table: RXTX_BITSLICE Ports, Table: RX_BITSLICE Ports, Table: TX_BITSLICE Ports, and Table: BITSLICE_CONTROL Ports.

Note:   Because the new Chapter 2 organization changed or deleted previous figure and table numbers, references in subsequent rows of this revision history table were accurate as of the date the version was printed.

Chapter 3: Updated HD I/O Bank Features and HD I/O Interface Logic.



Added the Virtex® UltraScale+™ family, the Kintex® UltraScale+ family, and Zynq® UltraScale+ MPSoCs to this user guide.

Chapter 1: Added IBUFDS_DPHY, OBUFDS_DPHY, and MIPI D-PHY sections. Updated the OBUFDS_DPHY slew rate in Table: Allowed Attributes for the MIPI_DPHY_DCI Standard . Added the MIPI_DPHY_DCI standard with Note 5 to Table: VCCO and VREF Requirements for Each Supported I/O Standard. Added the MIPI_DPHY_DCI standard with Note 6 to Table: Attribute Options, Bidirectional Buffer Availability, and DCI Termination Type and changed the MIPI slew rate to FAST.

Chapter 2: Updated This Figure, This Figure, and This Figure.

Added High Density I/O Resources and all references to HD I/O.



Note:   Table and figure numbers were accurate for the 1.4 version.

Chapter 1: Added Internal Differential Termination Behavior in Differential I/O Standards section.

Chapter 2: Updated the description in the IDELAYE3 section. Updated the RST port description in Table 2-11 and Table 2-15. Updated the Q[7:0] description in Table 2-18 and Table 2-22. Reversed the arrow direction for DATAOUT in Figure 2-22. Added TX_RST to Figure 2-34. In the introduction to Figure 2-36, changed T_BYTE_IN to T_BYTE_IN[3:0]. Updated RIU_VALID pin descriptions in Table 2-26 and Table 2-28. In Table 2-33, bypass 15:9 is no longer supported. Updated Component Mode Reset Sequence. Updated Native Mode Reset Sequence and removed the Native Mode BITSLICE Sequence figure. Updated Figure 2-12, OSERDES Used in SDR Mode. Updated FIFO. Resequenced Table 2-18, Table 2-20, Table 2-22, and Table 2-24 to match their preceding figures. Updated data type in Figure 2-47. Updated BITSLICE numbering in Figure 2-50.



Note:    Table and figure numbers were accurate for the 1.3 version.

In Chapter 1: Updated Supply Voltages for the SelectIO Pins section. Added State of I/Os During and After Configuration section. Updated Special DCI Requirements in Some Banks. Corrected Figure 1-28. Updated the VREF and Internal VREF sections. Updated the Transmitter Pre-Emphasis and LVDS Transmitter Pre-Emphasis sections. Added DATA_RATE section. Added Note 6 to Table 1-51. Added slew to Table 1-52 and Table 1-53. Updated Table 1-55 (added Note 4 and Note 5). Updated Table 1-56 and added Table 1-57. Added clarification to the text before the following tables and updated the tables: Table 1-59, Table 1-61, Table 1-63, Table 1-65, Table 1-67, Table 1-69, Table 1-71, Table 1-73, and Table 1-77.

A complete rewrite of Chapter 2 including adding sections on the Register Interface Unit, Built-In Self-Calibration (BISC), and Clocking Considerations.



Note:    Table, figure, and page numbers were accurate for the 1.2 version.

Clarified sections of the SelectIO Resources Introduction and the IBUF_ANALOG description under SelectIO Primitives. Removed RTT_NONE from some possible values for ODT for split-termination DCI on page 28 and page 32. Added Note 1 to Table 1-12. Updated the description under HSUL_12 and DIFF_HSUL_12. Revised the HSUL_12 ODT description in Table 1-48. Moved Table 1-52 and Table 1-53. Added Note 3 to Table 1-55.

Updated REFCLK_FREQUENCY in Table 2-12. Updated REFCLK in Table 2-17. Revised the DDR modes in Table 2-5. Updated REFCLK_FREQUENCY in Table 2-16. Removed the DDR 2:1 ratio in Table 2-8. In Table 2-27, updated CTRL_CLK. Updated REFCLK_FREQUENCY in Table 2-19.



Note:   Table and figure numbers were accurate for the 1.1 version. Added features to Table 1-1 and Note 3. Revised the Differences from Previous Generations section. Added clarification to various sections with regards to the OUTPUT_IMPEDANCE attribute. Updated the default for the DCIUpdateMode option to ASREQUIRED. An example discussion added below Table 1-9. Removed VREF tuning from the IBUFDSE3 and IOBUFDSE3 primitives. Added IBUF_ANALOG, IOBUF_INTERMDISABLE, and IBUFDS_DIFF_OUT_INTERMDISABLE to SelectIO Primitives, page 42. Throughout Chapter 1, removed IBUFG (clock input buffer) and updated Figure 1-18, removed IBUFGDS (differential clock input buffer) and updated Figure 1-22, and removed IBUFGDS_DIFF_OUT (differential clock input buffer with complementary outputs) and updated Figure 1-23.

Updated the descriptions and some figures and tables: IBUF_IBUFDISABLE, IBUF_INTERMDISABLE, IBUFE3, IBUFDS_DIFF_OUT_IBUFDISABLE, IBUFDS_IBUFDISABLE, IBUFDS_INTERMDISABLE, IBUFDSE3, IOBUF_DCIEN, IOBUFE3, IOBUFDS, IOBUFDS_DCIEN, IOBUFDS_DIFF_OUT, IOBUFDS_DIFF_OUT_DCIEN, IOBUFDS_INTERMDISABLE, IOBUFDS_DIFF_OUT_INTERMDISABLE, IOBUFDSE3, HPIO_VREF, IBUF_LOW_PWR Attribute, Output Slew Rate Attributes, Differential Termination Attribute, Internal VREF, DQS_BIAS, Transmitter Pre-Emphasis, LVDS Transmitter Pre-Emphasis, Receiver EQUALIZATION, LVDCI (Low-Voltage Digitally Controlled Impedance), HSLVDCI (High-Speed LVDCI), HSTL (High-Speed Transceiver Logic), Table 1-49, Table 1-50, Table 1-52, Table 1-53, Table 1-56, and Figure 1-83.

Added IBUFDS_DIFF_OUT_IBUFDISABLE, IOBUF_INTERMDISABLE, Source Termination Attribute (OUTPUT_IMPEDANCE), Table 1-13, Table 1-14, and VREF_CNTR.

Added the MEDIUM attribute to the HP I/O bank primitives in Table 1-20, Table 1-21, Table 1-22, Table 1-24, Table 1-36, Table 1-37, Table 1-44, Table 1-45, Table 1-48, Table 1-51, and Table 1-78. Updated columns in Table 1-55. Added clarifications to the DQS_BIAS discussion on page 127. Removed SUB_LVDS_25 and replaced with SUB_LVDS on page 132 and throughout the remaining tables including Table A-1. Removed attributes from Table 1-73. Updated the discussion in Rules for Combining I/O Standards in the Same Bank. Added Note 3 and Note 4 to Table 1-77. Added Note 5 to Table 1-78. See Chapter 2 revisions on next page.

Updated Figure 2-2. Updated the IDELAYE3 and ODELAYE3 discussions. Updated Table 2-17 and Table 2-1. In Table 2-12, Table 2-16, Table 2-19, and Table 2-21, clarified descriptions for DELAY_VALUE (DELAY_VALUE_EXT), DELAY_FORMAT, and UPDATE_MODE. In Table 2-7, updated the DATA_WIDTH description. Updated the SerDes Output Data Bits to Use in Table 2-5. Added Type column to Table 2-16 and Table 2-4. In Table 2-28, updated the RIU_VALID port description and the port widths and descriptions for the BIT_CTRL ports. In Table 2-27, updated the SERIAL_MODE description, the READ_IDLE_COUNT[5:0] default value, the ROUNDING_FACTOR type, CTRL_CLK, and added new attributes: SELF_CALIBRATE, IDLY_VT_TRACK, ODLY_VT_TRACK, QDLY_VT_TRACK, and RXGATE_EXTEND. Updated Figure 2-24. Removed the CLK_OUT port from Table 2-18 and updated RX_BIT_CTRL_IN[39:0], through TX_BIT_CTRL_OUT[39:0]. In Table 2-19, updated values for DELAY_VALUE, REFCLK_FREQUENCY, DATA_WIDTH, and added the UPDATE_MODE_EXT attribute. Updated Figure 2-29. In Table 2-20, updated the BITSLICE_CONTROL ports. Table 2-21, updated values for DELAY_VALUE, REFCLK_FREQUENCY, and added the ENABLE_PRE_ EMPHASIS attribute.



Initial Xilinx release.