Rules for Combining I/O Standards in the Same Bank

UltraScale Architecture SelectIO Resources User Guide (UG571)

Document ID
UG571
Release Date
2022-08-31
Revision
1.14 English

The following rules must be obeyed to combine different input, output, and bidirectional standards in the same bank:

1.Combining output standards only. Output standards with the same output VCCO requirement can be combined in the same bank.

Compatible example:

SSTL15_I and LVDCI_15 outputs

Incompatible example:

SSTL15 (output VCCO = 1.5V) and LVCMOS18 (output VCCO = 1.8V) outputs

Only two true differential output I/O standards can be combined in HR I/O banks. LVDS_25 with LVDS_PRE_EMPHASIS = FALSE (default) and LVDS_25 with LVDS_PRE_EMPHASIS = TRUE are considered as two different true-differential output standards in HR I/O banks.

Only one true differential output I/O standard can be used in HP I/O banks. LVDS with LVDS_PRE_EMPHASIS = FALSE (default) and LVDS with LVDS_PRE_EMPHASIS = TRUE are considered as two different true-differential output standards and cannot be combined within the same HP I/O bank.

2.Combining input standards only. Input standards with the same VCCO and VREF requirements can be combined in the same bank.

Compatible example:

LVCMOS15 and HSTL_II inputs

Incompatible example:

LVCMOS15 (input VCCO = 1.5V) and LVCMOS18 (input VCCO = 1.8V) inputs

Incompatible example:

HSTL_I_DCI_18 (VREF = 0.9V) and HSTL_I_DCI (VREF = 0.75V) inputs

3.Combining input standards and output standards. Input standards and output standards with the same VCCO requirement can be combined in the same bank.

Compatible example:

LVDS_25 output and LVCMOS25 input

Incompatible example:

LVDS_25 output (output VCCO = 2.5V) and HSTL_I input (input VCCO = 1.5V)

4.Combining bidirectional standards with input or output standards. When combining bidirectional I/O with other standards, make sure the bidirectional standard can meet the first three rules.

The implementation tools enforce these design rules.

Table: VCCO and VREF Requirements for Each Supported I/O Standard, summarizes the VCCO and VREF requirements for each supported I/O standard. For more detailed DC specifications, including the recommended operating ranges of the supplies for each supported I/O standard, see the specific UltraScale device data sheet [Ref 2].

Table 1-77:      VCCO and VREF Requirements for Each Supported I/O Standard

I/O Standard

I/O Bank Availability

VCCO (V)

VREF (V)

Output

Input

Input with DIFF_TERM_ADV and DIFF_TERM Support

Input

LVTTL

HR

3.3

3.3

N/A

N/A

LVCMOS33

HR

3.3

3.3

N/A

N/A

LVCMOS25

HR

2.5

2.5

N/A

N/A

LVCMOS18

Both

1.8

1.8

N/A

N/A

LVCMOS15

Both

1.5

1.5

N/A

N/A

LVCMOS12

Both

1.2

1.2

N/A

N/A

HSUL_12

Both

1.2

1.2

N/A

0.60

LVDCI_18

HP

1.8

1.8

N/A

N/A

LVDCI_15

HP

1.5

1.5

N/A

N/A

HSUL_12_DCI

HP

1.2

1.2

N/A

0.60

HSLVDCI_18

HP

1.8

1.8

N/A

0.90

HSLVDCI_15

HP

1.5

1.5

N/A

0.75

HSTL_I

Both

1.5

1.5

N/A

0.75

HSTL_II

HR

1.5

1.5

N/A

0.75

HSTL_I_DCI

HP

1.5

1.5

N/A

0.75

HSTL_I_18

Both

1.8

1.8

N/A

0.90

HSTL_II_18

HR

1.8

1.8

N/A

0.90

HSTL_I_DCI_18

HP

1.8

1.8

N/A

0.90

HSTL_I_12

HP

1.2

1.2

N/A

0.60

HSTL_I_DCI_12

HP

1.2

1.2

N/A

0.60

SSTL18_I

Both

1.8

1.8

N/A

0.90

SSTL18_II

HR

1.8

1.8

N/A

0.90

SSTL15

Both

1.5

1.5

N/A

0.75

SSTL15_R

HR

1.5

1.5

N/A

0.75

SSTL135

Both

1.35

1.35

N/A

0.675

SSTL135_R

HR

1.35

1.35

N/A

0.675

SSTL12

Both

1.2

1.2

N/A

0.60

SSTL18_I_DCI

HP

1.8

1.8

N/A

0.90

SSTL15_DCI

HP

1.5

1.5

N/A

0.75

SSTL135_DCI

HP

1.35

1.35

N/A

0.675

SSTL12_DCI

HP

1.2

1.2

N/A

0.60

DIFF_HSTL_I

Both

1.5

1.5(2)

N/A

N/A

DIFF_HSTL_II

HR

1.5

1.5(2)

N/A

N/A

DIFF_HSTL_I_18

Both

1.8

1.8(2)

N/A

N/A

DIFF_HSTL_II_18

HR

1.8

1.8(2)

N/A

N/A

DIFF_SSTL18_I

Both

1.8

1.8(2)

N/A

N/A

DIFF_SSTL18_II

HR

1.8

1.8(2)

N/A

N/A

DIFF_SSTL15

Both

1.5

1.5(2)

N/A

N/A

DIFF_SSTL15_R

HR

1.5

1.5(2)

N/A

N/A

DIFF_SSTL135

Both

1.35

1.35(2)

N/A

N/A

DIFF_SSTL135_R

HR

1.35

1.35(2)

N/A

N/A

DIFF_SSTL12

Both

1.2

1.2(2)

N/A

N/A

DIFF_HSUL_12

Both

1.2

1.2(3)

N/A

N/A

DIFF_HSTL_I_DCI

HP

1.5

1.5

N/A

N/A

DIFF_HSTL_I_DCI_18

HP

1.8

1.8

N/A

N/A

DIFF_SSTL18_I_DCI

HP

1.8

1.8

N/A

N/A

DIFF_SSTL15_DCI

HP

1.5

1.5

N/A

N/A

DIFF_SSTL135_DCI

HP

1.35

1.35

N/A

N/A

DIFF_SSTL12_DCI

HP

1.2

1.2

N/A

N/A

DIFF_HSUL_12_DCI

HP

1.2

1.2

N/A

N/A

BLVDS_25

HR

2.5

Any

N/A

N/A

LVDS_25

HR

2.5(5)

2.5(1)

2.5

N/A

RSDS_25

HR

2.5(5)

2.5(1)

2.5

N/A

TMDS_33

HR

3.3

Any

N/A

N/A

MINI_LVDS_25

HR

2.5(5)

2.5(1)

2.5

N/A

PPDS_25

HR

2.5(5)

2.5(1)

2.5

N/A

LVDS

HP

1.8

1.8(1)

1.8

N/A

LVPECL

HR

N/A

Any

N/A

N/A

SLVS_400_18

HP

N/A

1.8(1)

1.8

N/A

SLVS_400_25

HR

N/A

2.5(1)

2.5

N/A

SUB_LVDS

Both

1.8

1.8(1)

1.8

N/A

DIFF_HSTL_I_12

HP

1.2

1.2(2)

N/A

N/A

DIFF_POD10

HP

1.0

1.0(2)

N/A

N/A

DIFF_POD12

HP

1.2

1.2(2)

N/A

N/A

DIFF_HSTL_I_DCI_12

HP

1.2

1.2

N/A

N/A

DIFF_POD10_DCI

HP

1.0

1.0

N/A

N/A

DIFF_POD12_DCI

HP

1.2

1.2

N/A

N/A

POD10

HP

1.0

1.0

N/A

0.70

POD12

HP

1.2

1.2

N/A

0.84

POD10_DCI

HP

1.0

1.0

N/A

0.70

POD12_DCI

HP

1.2

1.2

N/A

0.84

MIPI_DPHY_DCI

HP(4)

1.2

1.2

1.2

N/A

Notes:

1.Differential inputs for these standards can be placed in banks with VCCO levels that are different from the required level for outputs. Some important criteria to consider:

a.The optional internal differential termination is not used, DIFF_TERM_ADV = TERM_NONE or DIFF_TERM = FALSE (default value), unless the VCCO voltage is at the level required for outputs.

b.The differential signals at the input pins meet the VIN requirements in the Recommended Operating Conditions table of the specific UltraScale device data sheet [Ref 2].

c.The differential signals at the input pins meet the VIDIFF and VICM requirements in the DC Specifications tables in the specific UltraScale device data sheet [Ref 2]. In some cases, to accomplish this it might be necessary to provide an external circuit to both AC-couple and DC-bias the pins.

2.When on-die input termination is used (ODT is set to a value other than RTT_NONE) or when DQS_BIAS = TRUE, the VCCO input voltage is as specified. When ODT = RTT_NONE and DQS_BIAS = FALSE, the VCCO input voltage is any allowed voltage.

3.When on-die input termination is used (ODT value set to something other than RTT_NONE) or when DQS_BIAS is set to TRUE, the VCCO input voltage is 1.2V for HP I/O banks. In HR I/O banks, when DQS_BIAS = FALSE, or in HP I/O banks when ODT = RTT_NONE, the VCCO input voltage is any allowed voltage.

4.The DPHY_DCI I/O standard is only supported in Virtex UltraScale+, Kintex UltraScale+, and Zynq UltraScale+ devices.

5.If the VCCO voltage exceeds 2.85V, the outputs are 3-stated. The device should always be operated within the recommended operating range as specified in the UltraScale device data sheets [Ref 2].

Table: Attribute Options, Bidirectional Buffer Availability, and DCI Termination Type, summarizes the DRIVE and SLEW attribute options, bidirectional buffer availability, and DCI termination type for each supported I/O standard.

Table 1-78:      Attribute Options, Bidirectional Buffer Availability, and DCI Termination Type

I/O Standard

I/O Bank Type

Output Slew

Output Drive

Bidirectional Buffers(1)

Termination Type(2)

HR I/O Banks

HP I/O Banks

HR I/O Banks

HP I/O Banks

Input

Output (3)

Allowed Values

Default

Allowed Values

Default

Allowed Values

Default

Allowed Values

Default

LVTTL

HR

SLOW FAST

SLOW

N/A

4, 8, 12, 16

12

N/A

Yes

None

None

LVCMOS33

HR

SLOW FAST

SLOW

N/A

4, 8, 12, 16

12

N/A

Yes

None

None

LVCMOS25

HR

SLOW FAST

SLOW

N/A

4, 8, 12, 16

12

N/A

Yes

None

None

LVCMOS18

Both

SLOW FAST

SLOW

SLOW
MEDIUM
FAST

SLOW

4, 8, 12, 16

12

2, 4, 6, 8, 12

12

Yes

None

None

LVCMOS15

Both

SLOW FAST

SLOW

SLOW
MEDIUM
FAST

SLOW

4, 8, 12, 16

12

2, 4, 6, 8, 12

12

Yes

None

None

LVCMOS12

Both

SLOW FAST

SLOW

SLOW
MEDIUM
FAST

SLOW

4, 8, 12

12

2, 4, 6, 8

12

Yes

None

None

HSUL_12

Both

SLOW FAST

SLOW

SLOW
MEDIUM
FAST

SLOW

N/A

N/A

Yes

Single(4)

Driver(4)

LVDCI_18

HP

N/A

SLOW
MEDIUM
FAST

SLOW

N/A

N/A

Yes

None

Driver

LVDCI_15

HP

N/A

SLOW
MEDIUM
FAST

SLOW

N/A

N/A

Yes

None

Driver

HSUL_12_DCI

HP

N/A

SLOW
MEDIUM
FAST

SLOW

N/A

N/A

Yes

Single

Driver

HSLVDCI_18

HP

N/A

SLOW
MEDIUM
FAST

SLOW

N/A

N/A

Yes

None

Driver

HSLVDCI_15

HP

N/A

SLOW
MEDIUM
FAST

SLOW

N/A

N/A

Yes

None

Driver

HSTL_I

Both

SLOW FAST

SLOW

SLOW
MEDIUM
FAST

SLOW

N/A

N/A

Yes

Split

Driver

HSTL_II

HR

SLOW FAST

SLOW

N/A

N/A

N/A

Yes

Split

None

HSTL_I_DCI

HP

N/A

SLOW
MEDIUM
FAST

SLOW

N/A

N/A

Yes

Split

Driver

HSTL_I_18

Both

SLOW FAST

SLOW

SLOW
MEDIUM
FAST

SLOW

N/A

N/A

Yes

Split

Driver

HSTL_II_18

HR

SLOW FAST

SLOW

N/A

 

N/A

N/A

Yes

Split

None

HSTL_I_DCI_18

HP

N/A

SLOW
MEDIUM
FAST

SLOW

N/A

N/A

Yes

Split

Driver

HSTL_I_12

HP

N/A

SLOW
MEDIUM
FAST

SLOW

N/A

N/A

Yes

Split

Driver

HSTL_I_DCI_12

HP

N/A

SLOW
MEDIUM
FAST

SLOW

N/A

N/A

Yes

Split

(UltraScale devices only)

Driver

SSTL18_I

Both

SLOW FAST

SLOW

SLOW
MEDIUM
FAST

SLOW

N/A

N/A

Yes

Split

Driver

SSTL18_II

HR

SLOW FAST

SLOW

N/A

N/A

N/A

Yes

Split

None

SSTL15

Both

SLOW FAST

SLOW

SLOW
MEDIUM
FAST

SLOW

N/A

N/A

Yes

Split

Driver

SSTL15_R

HR

SLOW FAST

SLOW

N/A

N/A

N/A

Yes

Split

None

SSTL135

Both

SLOW FAST

SLOW

SLOW
MEDIUM
FAST

SLOW

N/A

N/A

Yes

Split

Driver

SSTL135_R

HR

SLOW FAST

SLOW

N/A

N/A

N/A

Yes

Split

None

SSTL12

Both

SLOW FAST

SLOW

SLOW
MEDIUM
FAST

SLOW

N/A

N/A

Yes

Split

Driver

SSTL18_I_DCI

HP

N/A

SLOW
MEDIUM
FAST

SLOW

N/A

N/A

Yes

Split

Driver

SSTL15_DCI

HP

N/A

SLOW
MEDIUM
FAST

SLOW

N/A

N/A

Yes

Split

Driver

SSTL135_DCI

HP

N/A

SLOW
MEDIUM
FAST

SLOW

N/A

N/A

Yes

Split

Driver

SSTL12_DCI

HP

N/A

SLOW
MEDIUM
FAST

SLOW

N/A

N/A

Yes

Split

Driver

DIFF_HSTL_I

Both

SLOW FAST

SLOW

SLOW
MEDIUM
FAST

SLOW

N/A

N/A

Yes

Split

Driver

DIFF_HSTL_II

HR

SLOW FAST

SLOW

N/A

N/A

N/A

Yes

Split

None

DIFF_HSTL_I_18

Both

SLOW FAST

SLOW

SLOW
MEDIUM
FAST

SLOW

N/A

N/A

Yes

Split

Driver

DIFF_HSTL_II_18

HR

SLOW FAST

SLOW

N/A

N/A

N/A

Yes

Split

None

DIFF_SSTL18_I

Both

SLOW FAST

SLOW

SLOW
MEDIUM
FAST

SLOW

N/A

N/A

Yes

Split

Driver

DIFF_SSTL18_II

HR

SLOW FAST

SLOW

N/A

N/A

N/A

Yes

Split

None

DIFF_SSTL15

Both

SLOW FAST

SLOW

SLOW
MEDIUM
FAST

SLOW

N/A

N/A

Yes

Split

Driver

DIFF_SSTL15_R

HR

SLOW FAST

SLOW

N/A

N/A

N/A

Yes

Split

None

DIFF_SSTL135

Both

SLOW FAST

SLOW

SLOW
MEDIUM
FAST

SLOW

N/A

N/A

Yes

Split

Driver

DIFF_SSTL135_R

HR

SLOW FAST

SLOW

N/A

N/A

N/A

Yes

Split

None

DIFF_SSTL12

Both

SLOW FAST

SLOW

SLOW
MEDIUM
FAST

SLOW

N/A

N/A

Yes

Split

Driver

DIFF_HSUL_12

Both

SLOW FAST

SLOW

SLOW
MEDIUM
FAST

SLOW

N/A

N/A

Yes

Single(4)

Driver(4)

DIFF_HSTL_I_DCI

HP

N/A

SLOW
MEDIUM
FAST

SLOW

N/A

N/A

Yes

Split

Driver

DIFF_HSTL_I_DCI_18

HP

N/A

SLOW
MEDIUM
FAST

SLOW

N/A

N/A

Yes

Split

Driver

DIFF_SSTL18_I_DCI

HP

N/A

SLOW
MEDIUM
FAST

SLOW

N/A

N/A

Yes

Split

Driver

DIFF_SSTL15_DCI

HP

N/A

SLOW
MEDIUM
FAST

SLOW

N/A

N/A

Yes

Split

Driver

DIFF_SSTL135_DCI

HP

N/A

SLOW
MEDIUM
FAST

SLOW

N/A

N/A

Yes

Split

Driver

DIFF_SSTL12_DCI

HP

N/A

SLOW
MEDIUM
FAST

SLOW

N/A

N/A

Yes

Split

Driver

DIFF_HSUL_12_DCI

HP

N/A

SLOW
MEDIUM
FAST

SLOW

N/A

N/A

Yes

Single

Driver

BLVDS_25

HR

N/A

N/A

N/A

N/A

Yes

None

None

LVDS_25

HR

N/A

N/A

N/A

N/A

Yes(5)

None

None

RSDS_25

HR

N/A

N/A

N/A

N/A

Yes(5)

None

None

TMDS_33

HR

N/A

N/A

N/A

N/A

Yes(5)

None

None

MINI_LVDS_25

HR

N/A

N/A

N/A

N/A

Yes(5)

None

None

PPDS_25

HR

N/A

N/A

N/A

N/A

Yes(5)

None

None

LVDS

HP

N/A

N/A

N/A

N/A

Yes(5)

None

None

LVPECL

HR

N/A

N/A

N/A

N/A

No

None

None

SLVS_400_18

HP

N/A

N/A

N/A

N/A

No

None

None

SLVS_400_25

HR

N/A

N/A

N/A

N/A

No

None

None

SUB_LVDS

Both

N/A

N/A

N/A

N/A

Yes(5)

None

None

DIFF_HSTL_I_12

HP

N/A

SLOW
MEDIUM
FAST

SLOW

N/A

N/A

Yes

Split

Driver

DIFF_POD10

HP

N/A

SLOW
MEDIUM
FAST

SLOW

N/A

N/A

Yes

Single

Driver

DIFF_POD12

HP

N/A

SLOW
MEDIUM
FAST

SLOW

N/A

N/A

Yes

Single

Driver

DIFF_HSTL_I_DCI_12

HP

N/A

SLOW
MEDIUM
FAST

SLOW

N/A

N/A

Yes

Split

(UltraScale devices only)

Driver

DIFF_POD10_DCI

HP

N/A

SLOW
MEDIUM
FAST

SLOW

N/A

N/A

Yes

Single

Driver

DIFF_POD12_DCI

HP

N/A

SLOW
MEDIUM
FAST

SLOW

N/A

N/A

Yes

Single

Driver

POD10

HP

N/A

SLOW
MEDIUM
FAST

SLOW

N/A

N/A

Yes

Single

Driver

POD12

HP

N/A

SLOW
MEDIUM
FAST

SLOW

N/A

N/A

Yes

Single

Driver

POD10_DCI

HP

N/A

SLOW
MEDIUM
FAST

SLOW

N/A

N/A

Yes

Single

Driver

POD12_DCI

HP

N/A

SLOW
MEDIUM
FAST

SLOW

N/A

N/A

Yes

Single

Driver

MIPI_DPHY_DCI

HP(6)

N/A

N/A

N/A

N/A

N/A

No

N/A

Driver

Notes:

1.The bidirectional buffers column describes the I/O standards use of a bidirectional signal.

2.The DCI termination type column describes the type of termination available for the DCI I/O standards. Split refers to the split-termination resistors. Single refers to single resistor termination to VCCO.

3.A value of DRIVER in this column only applies to HP I/O banks

4.INTERM = Single and OUTTERM = DRIVER for HP I/O banks, INTERM = NONE and OUTTERM = NONE for HR I/O banks.

5.The bidirectional configuration on these I/O standards is a fixed impedance structure optimized to 100W differential. They are intended to only be used in point-to-point transmissions that do not have turn around timing requirements. Use BLVDS_25 for bus structures.

6.The MIPI_DPHY_DCI standard is only supported in Virtex UltraScale+, Kintex UltraScale+, and Zynq UltraScale+ devices.

T