SAME_EDGE_PIPELINED Mode

UltraScale Architecture SelectIO Resources User Guide (UG571)

Document ID
UG571
Release Date
2022-08-31
Revision
1.14 English

In SAME_EDGE_PIPELINED mode, the data is presented into the device logic on the same clock edge. Unlike the SAME_EDGE mode, the data pair is not separated by one clock cycle. However, additional clock latency is required to remove the separated effect of the SAME_EDGE mode. This Figure shows the timing diagram of the input DDR using the SAME_EDGE_PIPELINED mode. The output pairs Q1 and Q2 are presented to the device logic at the same time.

Figure 2-6:      Input DDR Timing in SAME_EDGE_PIPELINED Mode

X-Ref Target - Figure 2-6

X16007-input-ddr-timing-in-same_edge_pipelined-mode.jpg

This Figure shows a block diagram of the IDDRE1 primitive.

Figure 2-7:      IDDRE1 Primitive Block Diagram

X-Ref Target - Figure 2-7

X16008-iddre1-primitive-block-diag.jpg