SSTL15_DCI, SSTL135_DCI, SSTL12_DCI, DIFF_SSTL15_DCI, DIFF_SSTL135_DCI, DIFF_SSTL12

SSTL15_DCI, SSTL135_DCI, SSTL12_DCI, DIFF_SSTL15_DCI, DIFF_SSTL135_DCI, DIFF_SSTL12_DCI

UltraScale Architecture SelectIO Resources User Guide (UG571)

Document ID

UG571

Release Date

2022-08-31

Revision

1.14 English

Table 1-43: Available I/O Bank Type
HR	HP
N/A	Available

The DCI standards provide tuned internal parallel split-termination resistors that are always present at the receivers. The value of both the resistance set by the ODT attributes, creates the Thevenin equivalent of R (where R = Z₀) to the V_CCO/2 mid-point level. The source termination feature (OUTPUT_IMPEDANCE) provides the option of 40W, 48W, or 60W tuned driver impedance in HP I/O banks. The driver output impedance is set to a default of 40W. The differential (DIFF_) versions use complementary single-ended drivers for outputs, and differential receivers for inputs.