SSTL18, SSTL15, SSTL135, SSTL12

UltraScale Architecture SelectIO Resources User Guide (UG571)

Document ID
UG571
Release Date
2022-08-31
Revision
1.14 English

This Figure shows a sample circuit illustrating a unidirectional termination technique for SSTL18, SSTL15, SSTL135, or SSTL12. In a specific circuit, all drivers and receivers must be at the same voltage level (1.8V, 1.5V, 1.35V, or 1.2V); they are not interchangeable (i.e., SSTL12 should only interface with SSTL12).

Figure 1-64:      SSTL18, SSTL15, SSTL135, or SSTL12 Unidirectional Termination

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This Figure shows a sample circuit illustrating a bidirectional termination technique for SSTL18, SSTL15, SSTL135, or SSTL12. In a specific circuit, all drivers and receivers must be at the same voltage level (1.8V, 1.5V, 1.35V, or 1.2V); they are not interchangeable (i.e., SSTL12 should only interface with SSTL12).

Figure 1-65:      SSTL18, SSTL15, SSTL135, or SSTL12 Bidirectional Termination

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This Figure shows a sample circuit illustrating a bidirectional termination technique for SSTL18, SSTL15, SSTL135, or SSTL12 with DCI. In a specific circuit, all drivers and receivers must be at the same voltage level (1.8V, 1.5V, 1.35V, or 1.2V); they are not interchangeable (i.e., SSTL12_DCI should only interface with SSTL2_DCI). DCI standards are only supported in HP I/O banks.

Figure 1-66:      SSTL18_DCI, SSTL15_DCI, SSTL135_DCI, or SSTL12_DCI Bidirectional Termination

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