SSTL18_II, SSTL15_R, SSTL135_R, DIFF_SSTL18_II, DIFF_SSTL15_R, DIFF_SSTL135_R

UltraScale Architecture SelectIO Resources User Guide (UG571)

Document ID
UG571
Release Date
2023-08-31
Revision
1.15 English
Table 1-41: Available I/O Bank Type

HR

HP

Available

Not Available

Parallel end-termination resistors (commonly 50 ) to V TT = (V CCO /2) are typically placed on the board close to any receiver. Depending on the board topology, source-termination series resistors help match the output driver impedance to the transmission line and end-termination impedances, to reduce reflections and improve signal integrity. Optional untuned split input ODT provides Thevenin equivalent resistance of R (where R = Z 0 ) to the V CCO /2. The differential (DIFF_) versions use complementary single-ended drivers for outputs, and differential receivers for inputs.