SelectIO Technology Resources Introduction

UltraScale Architecture SelectIO Resources User Guide (UG571)

Document ID
UG571
Release Date
2022-08-31
Revision
1.14 English

All UltraScale devices have configurable SelectIO interface drivers and receivers, supporting a wide variety of standard interfaces. The robust feature set includes programmable control of output strength and slew rate, on-chip termination using digitally controlled impedance (DCI), and the ability to internally generate a reference voltage (INTERNAL_VREF).

 

IMPORTANT:   HR I/O banks do not have DCI. Therefore, any reference to DCI in this user guide does not apply to the HR I/O banks.

With some exceptions, each I/O bank contains 52 SelectIO pins, where 48 can implement both single-ended and differential I/O standards. The other four pins, including the multipurpose VRP pin, are single-ended (only) IOBs. Every SelectIO resource contains input, output, and 3-state drivers.

The SelectIO pins can be configured to various I/O standards, both single-ended and differential.

Single-ended I/O standards are, for example, LVCMOS, LVTTL, HSTL, SSTL, HSUL, and POD.

Differential I/O standards are, for example, LVDS, Mini_LVDS, RSDS, PPDS, BLVDS, TMDS, SLVS, LVPECL, SUB_LVDS, and differential HSTL, POD, HSUL, and SSTL.

When not used as a VRP pin, the multipurpose VRP pin in each bank can only be used with single-ended I/O standards. This Figure shows the single-ended (only) HP I/O block (IOB) and its connections to the internal logic and the device pad. This Figure shows the standard HP IOB. This Figure shows the single-ended (only) HR IOB. This Figure shows the standard HR IOB. This Figure shows the relative location of the single-ended IOBs within a bank. When not configured, I/O drivers are 3-stated and I/O receivers are weakly pulled-down.

Each IOB has a direct connection to bit slice components containing the input and output resources for serialization, deserialization, signal delay, clock, data, and 3-state control, and registering for the IOB. The bit slice components can be used in Component mode individually as IDELAY, ODELAY, ISERDES, OSERDES, and input and output registers. They can also be used at a lower granularity level as RX_BITSLICE (input), TX_BITSLICE (output), and RXTX_BITSLICE (bidirectional) components where all of the bit slice functions are grouped together in a single interface. See SelectIO Interface Logic Resources for more information.

Figure 1-1:      Single-Ended (Only) HP IOB Diagram

X-Ref Target - Figure 1-1

X16145-single-ended-hp-iob-diag.jpg
Figure 1-2:      Standard HP IOB Diagram

X-Ref Target - Figure 1-2

X16060-standard-hb-iob-diag.jpg
Figure 1-3:      Single-Ended (Only) HR IOB Diagram

X-Ref Target - Figure 1-3

X16061-single-ended-only-hr-iob-diag.jpg
Figure 1-4:      Standard HR IOB Diagram

X-Ref Target - Figure 1-4

X16062-standard-hr-iob-diag.jpg
Figure 1-5:      Relative Single-Ended I/O Locations within an HR or HP I/O Bank

X-Ref Target - Figure 1-5

X16063-relative-single-ended-io-locations-within-an-hr-or-hp-io-bank.jpg