Step 1: Alignment

UltraScale Architecture SelectIO Resources User Guide (UG571)

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1.14 English

Alignment is the first step in the BISC process and is necessary to maximize the data eye in the bit slices by removing internal skew and compensating for the internal skew between clock and data insertion delays of input paths to first capture flip-flops.

Note:   PCB (trace) delay, package influences on the input signals, and deskewing of output signals are not handled by the BISC.

This delay is called Align_Delay and is used in the calculations provided in the “Native Delay Mode Usage” paragraph. This delay typically takes between 45 and 65 taps of the input delay line.

This step also manages possible duty cycle distortion (DCD) and the initial voltage and temperature calibration of the data and capture clock signals.