Step 2: Delay Calibration

UltraScale Architecture SelectIO Resources User Guide (UG571)

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1.14 English

This step walks through the input and/or output delay of each used bit slice to calculate the number of taps required to provide the delay requested by DELAY_VALUE attribute. These calculated delay taps are stored in the RIU registers (ODELAYxx and IDELAYxx). The same is done for the BITSLICE_CONTROL available quarter delay lines (PQTR/NQTR) to provide the 90-degree equivalent delay when RX_CLK_PHASE_P(N) = SHIFT_90. These values are stored in the RIU PQTR and NQTR registers.

The BISC controller signals the interconnect logic when the delay line calibration mechanism for all used bit slices is done by asserting the DLY_RDY signal.