Step 3: Continuous VT Tracking

UltraScale Architecture SelectIO Resources User Guide (UG571)

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1.14 English

When turned on by an attribute or RIU register, at this step the BISC controller starts a continuous operation of the last step in the calibration part of BISC, VT tracking.

The automated tracking uses a round-robin scheme to keep every used delay line up to date without interfering or disrupting the normal operation mode of that bit slice.

During calibration, the BISC can modify or write to certain RIU registers. The register values altered by BISC include TX_DATA_PHASE, BS_DQ_EN, BS_DQS_EN, EN_PDQS, EN_NDQS, INVERT_RX_CLK, SERIAL_MODE, TX_GATE, and RX_GATE.

Each nibble has its own BITSLICE_CONTROL component and therefore its own BISC controller. When multiple nibbles or bytes are used and have shared clocks through the inter-nibble or inter-byte clock resources, each nibble can calibrate the bit slices used in that nibble. Each nibble can require different times to finish the same calibration step due to different environments and configurations. Through inter-nibble or inter-byte communication, each nibble should not proceed to the next calibration step until all nibbles finish the current calibration step.

Note:   The reset for all used BITSLICE_CONTROLs within a bank must be released at the same time due to the DLY_RDY connections between the BITSLICE_CONTROLs. For example, if a bank has two different interfaces, both interfaces should be controlled by a single reset to ensure calibration completes. Failure to do so might result in DLY_RDY for one of the interfaces not asserting.