TX_BITSLICE Attributes

UltraScale Architecture SelectIO Resources User Guide (UG571)

Document ID
UG571
Release Date
2022-08-31
Revision
1.14 English

Table: TX_BITSLICE Attributes lists the TX_BITSLICE attributes.

Table 2-27:      TX_BITSLICE Attributes

Attributes

Values

Default

Type

Description

DATA_WIDTH

4 or 8

8

Decimal

Attribute defining the input width of the parallel-to-serial converter.

This value specifies the width the data requires to be serialized by the parallel-to-serial converter. Set DATA_WIDTH = 2 x BITSLICE_CONTROLLER.DIV_MODE.

TBYTE_CTL

TBYTE_IN or T

TBYTE_IN

String

TBYTE_IN: The TBYTE_IN input is used to pass the 3-state information to the T_OUT output. It also requires that the TX_BITSLICE is used together with a TX_BITSLICE_TRI component.

T: The T input is used to pass the 3-state information to the T_OUT output. T requires that the 3-state information is generated in the interconnect logic. See the explanation in TX_BITSLICE_TRI.

INIT

1'b0 or 1'b1

1'b1

Binary

Defines the initial value of the O port, which is the serialized data output of the TX_BITSLICE.

DELAY_TYPE

FIXED VAR_LOAD VARIABLE

FIXED

String

Delay mode of the output delay line. For more information, see Native Output Delay Type Usage.

DELAY_VALUE

0–1250 (TIME UltraScale)

0–1100 (TIME UltraScale+)

0–511 (COUNT)

0

Decimal

Note:   For BISC to properly align, set RX_CLK_PHASE_P = RX_CLK_PHASE_N = SHIFT_0.

When DELAY_FORMAT is set to TIME mode, the desired value is in ps.

UltraScale devices support delays up to 1.25 ns. UltraScale+ devices support up to 1.1 ns.

When DELAY_FORMAT is set to COUNT mode, the desired value is in number of taps. For more information, see Native Output Delay Type Usage. To ensure TX_BITSLICE data alignment, limit COUNT delays to 1.5 UI.

REFCLK_FREQUENCY

200.00–2400.00 (UltraScale)

300.00–2666.67 (UltraScale+)

300.0

1 significant digit float

Specification of reference clock frequency in MHz.

This is the frequency of the master_clock that the BITSLICE_CONTROL is configured to use. It is used by BISC to calibrate any TIME mode delays. See Clocking in Native Mode and Built-in Self-Calibration. As opposed to previous FPGA families, the tap size is not determined by the REFCLK_FREQUENCY, the tap size is defined in the UltraScale device data sheets as TODELAY_RESOLUTION [Ref 2] and the REFCLK_FREQUENCY attribute is used by BISC to calibrate the amount of taps to provide the requested delay when DELAY_FORMAT is set to TIME mode.

OUTPUT_PHASE_90

TRUE or FALSE

FALSE

String

FALSE: Output O is not phase-shifted.

TRUE: Output O is phase-shifted 90 degrees. DELAY_VALUE must be set to 0 when OUTPUT_PHASE_90 = TRUE.

The phase shift can be observed when different transmitters are used. In most cases, it is used to shift the generated clock 90 degrees to the generated data (generated data and center-aligned clock).

DELAY_FORMAT

TIME(1)

COUNT

TIME

String

DELAY_FORMAT can be either TIME or COUNT.

When set to TIME, the delay after BISC completes (DLY_RDY goes High) equals the delay given in DELAY_VALUE (specified in ps).

BISC uses the REFCLK_FREQUENCY attribute in conjunction with the incoming master clock to determine how many taps are required to achieve the requested TIME value (DELAY_VALUE). This calibration accounts for the process variation in the device. When EN_VTC is High, the delay is calibrated to provide the requested TIME across voltage and temperature.

When DELAY_FORMAT is set to COUNT, the value given in DELAY_VALUE is the number of taps required. EN_VTC must be tied Low when using COUNT.

UPDATE_MODE

ASYNC, SYNC, or MANUAL

ASYNC

String

ASYNC: This is the default and preferred use method. Updates to the delay value are independent of the data being delayed. This mode is the preferred operation mode because it covers the function of both other modes.

SYNC: Updates require data transitions to synchronously update the delay with the data edges. This mode is suitable for clocks or data that are always available and switches on a periodic basis.

MANUAL: It takes two assertions of LOAD for the new value to take effect. The first LOAD loads the value defined by CNTVALUEIN and the second LOAD must be asserted with an assertion of the CE for the new value to take effect. This is beneficial because you can update the delay when the data becomes idle.

ENABLE_PRE_EMPHASIS

TRUE

FALSE

FALSE

String

Used in conjunction with attributes on the bidirectional IOB to enable and disable pre-emphasis. The ENABLE_PRE_EMPHASIS attribute is used in conjunction with IOB to enable the pre-emphasis. See Transmitter Pre-Emphasis.

IS_CLK_INVERTED

1'b0 or 1'b1

1'b0

Binary

Similar to the IS_RST_INVERTED attribute, but on the CLK path.

When IS_CLK_INVERTED = 1, the inverter is used to reverse polarity (invert) the CLK signal.

When IS_CLK_INVERTED = 0, the inverter is not used.

IS_RST_DLY_INVERTED

1'b0 or 1'b1

1'b0

Binary

Similar to the IS_RST_INVERTED attribute but on the RST_DLY path.

When IS_RST_DLY_INVERTED = 1, the inverter is used to reverse polarity (invert) the RST_DLY signal.

When IS_RST_DLY_INVERTED = 0, the inverter is not used.

IS_RST_INVERTED

1'b0 or 1'b1

1'b0

Binary

A selectable local inverter on the reset path can be used to change the polarity of the reset input.

When IS_RST_INVERTED = 1, the inverter is used to reverse the polarity (invert) the RST signal.

When IS_RST_INVERTED = 0, the inverter is not used. See This Figure.

NATIVE_ODELAY_BYPASS

TRUE or FALSE

FALSE

String

UltraScale+ FPGAs only: Reserved for memory interface generator (MIG). When TRUE, bypass the ODELAY.

SIM_DEVICE

Possible Values: ULTRASCALE, ULTRASCALE_PLUS, ULTRASCALE_PLUS_ES1, ULTRASCALE_PLUS_ES2

ULTRASCALE

String

Sets the device version (ULTRASCALE, ULTRASCALE_PLUS, ULTRASCALE_PLUS_ES1, ULTRASCALE_PLUS_ES2)

Notes:

1.When in TIME mode, calibration affects the availability of bit slices within the nibble. See Bank Overview for more information.