TX_BITSLICE Ports

UltraScale Architecture SelectIO Resources User Guide (UG571)

Document ID
UG571
Release Date
2022-08-31
Revision
1.14 English

Table: TX_BITSLICE Ports lists the TX_BITSLICE ports.

Table 2-26:      TX_BITSLICE Ports

Port

Function(1)

I/O

Synchronous Clock Domain

Description

D[7:0]

TX

FPGA

Input

PLL_CLK

(BITSLICE_CONTROL)

Parallel incoming data from interconnect logic for transmit. Width is determined by the DATA_WIDTH attribute and can be either 8 or 4. If the DATA_WIDTH is 4, D[3:0] is used and D[7:4] should be tied to 0.

T

TX

FPGA

Input

Asynchronous

T assigns a combinatorial path through the TX_BITSLICE to the 3-state pin of an output buffer.

When the 3-state control is sourced from the interconnect logic, the T port must be used. Use of the T input of a bit slice can be seen as a block 3-state of the serial bitstream.

Each TX_BITSLICE in a nibble has a T input, meaning that there are 13 T inputs for a byte (byte = two nibbles).

A logic High means the output buffer is 3-stated and a logic Low means the output buffer is not 3-stated. Active-High.

TBYTE_IN

TX

FPGA

Input

PLL_CLK

(BITSLICE_CONTROL)

The TBYTE_IN is 1-bit width wide input of the TX_BITSLICE side of the RXTX_BITSLICE. When using this 3-state, the TX_BITSLICE_TRI component must be used to serialize the TBYTE_IN[3:0] 3-state bus input of the BITSLICE_CONTROL, giving the ability to 3-state individual bits in the serial output data stream. The TBYTE_IN[3:0] port of the BITSLICE_CONTROL is handled and passes through the BITSLICE_CONTROL to connect to the TX_BITSLICE_TRI. The TRI_OUT then connects to each TX_BITSLICE.TBYTE_IN input port in the nibble. When the BITSLICE_CONTROL TBYTE_IN is High it means the output buffer is not 3-stated and a logic Low means the output buffer is 3-stated.

RST

TX

FPGA

Input

Asynchronous

Resets the transmit side (TX_BITSLICE), asynchronous assertion and synchronous deassertion and is active-High. O resets to the INIT attribute value while RST is asserted.

For deterministic bring-up, follow the steps in Native Mode Bring-up and Reset.

CLK

TX

FPGA

Input

Asynchronous

Delay line clock used to sample LOAD, CE, and INC. All control inputs to output delay line element within the TX part of the RXTX_BITSLICE are synchronous to the clock input (CLK). A clock must be connected to this port when the delay is configured in VARIABLE or VAR_LOAD. The CLK can be locally inverted, and must be supplied by a global clock buffer.

CE

TX

FPGA

Input

CLK

Clock enable for the output delay line register clock.

Note:   Delays might take up to three clock cycles (CLK) to be applied. During this time, input data should not change to ensure output data does not glitch.

RST_DLY

TX

FPGA

Input

Asynchronous

(synchronous deassertion to CLK)

Reset port for the delay line within the transmitter logic. Resets the internal delay line to the value defined in the DELAY_VALUE attribute.

INC

TX

FPGA

Input

CLK

The increment/decrement is controlled by the enable signal (CE). This interface is only available when the delay line is in VARIABLE or VAR_LOAD mode. As long as CE remains High, the delay line is incremented or decremented by one tap every clock (CLK) cycle. The state of INC determines whether the delay line is incremented or decremented: INC = 1 increments; INC = 0 decrements, synchronously to the clock (CLK). If CE is Low, the delay does not change (regardless of the state of INC). When CE goes High, the increment/decrement operation begins on the next positive clock edge. When CE goes Low, the increment/decrement operation ceases on the next positive clock edge.

The programmable delay taps in the delay line primitive wrap around. When the last tap delay is reached (CNTVALUEOUT = 511), a subsequent increment function returns to tap 0. The same applies to the decrement function: decrementing from zero moves to tap 511.

LOAD

TX

FPGA

Input

CLK

When in VAR_LOAD mode and UPDATE_MODE = ASYNC, this input loads the value set by the CNTVALUEIN into the delay line. The value present at CNTVALUEIN[8:0] is the new tap value. The LOAD signal is an active-High signal and is synchronous to the input clock signal (CLK). Wait at least one clock cycle after applying a new value on the CNTVALUEIN bus before applying the LOAD signal. The CE must be held Low during LOAD operation.

Note:   Delays might take up to three clock cycles (CLK) to be applied. During this time, input data should not change to ensure output data does not glitch.

EN_VTC

TX

FPGA

Input

Asynchronous

Enable voltage, temperature, and process compensation.

High: Allows BITSLICE_CONTROL to keep delay constant over VT. BITSLICE_CONTROL.EN_VTC must be High for VT compensation to be enabled.

Low: VT compensation is disabled.

When TIME mode is used, the EN_VTC signal must be pulled High during initial built-in self-calibration (BISC).

When used in COUNT mode, the EN_VTC signal must be pulled Low.

When bit slices are used in both COUNT and TIME mode in a nibble, EN_VTC must be pulled High for the bit slices used in TIME mode, and pulled High or Low for those used in COUNT mode.

CNTVALUEIN[8:0]

TX

FPGA

Input

CLK

The CNTVALUEIN bus is used for dynamically changing the loadable tap value. The 9-bit value at the CNTVALUEIN bus is the new tap value the delay line is set to after LOAD. Provide the value on this bus at least one clock cycle before LOAD. The delay line can be changed from 1 to 8 taps at a time.

Note:   When changing delays using the VT compensation using EN_VTC, only the programmed delay is compensated for. Applications requiring updated output delays to be compensated must use the RIU interface to program the input delays to match the output delays (see Table: Register Bit Description (ODELAYxx) and Table: Register Bit Description (IDELAYxx)).

CNTVALUEOUT[8:0]

TX

FPGA

Output

CLK

The CNTVALUEOUT pins are used for reporting the current tap value and reading out the amount of taps in the current delay. When EN_VTC is High, CNTVALUEOUT is updated by the BITSLICE_CONTROL.

O

I/O

TX

Output

PLL_CLK

(BITSLICE_CONTROL)

Serialized output data from the TX_BITSLICE that should be connected to the output buffer (or bidirectional buffer).

T_OUT

I/O

TX

Output

PLL_CLK (when TBYTE_CTL set to TBYTE_IN)

otherwise Asynchronous (BITSLICE_CONTROL)

3-state output from the TX_BITSLICE that should be connected to the output buffer (or bidirectional buffer). Can be either the combinatorial output when TBYTE_CTL is set to T or the serialized output when

TBYTE_CTL is set to TBYTE_IN.

The following RX/TX_BIT_CTRL_OUT and RX/TX_BIT_CTRL_IN pins are 40-bit bus connections between the RXTX_BITSLICE (RX_BITSLICE and/or TX_BITSLICE) and the BITSLICE_CONTROL. Each of these 40-bit buses carries data, clocks, RIU, and status signals between the RXTX_BITSLICE (RX_BITSLICE, TX_BITSLICE), TX_BITSLICE_TRI, and BITSLICE_CONTROL and vice versa.

When a bit slice is used, these buses must be connected to the appropriate BITSLICE_CONTROL input and output bus.

Example:

When RXTX_BITSLICE_2 is used, RX/TX_BIT_CTRL_OUT of that RXTX_BITSLICE must connect to the BITSLICE_CONTROL RX/TX_BIT_CTRL_IN2, and the RX/TX_BIT_CTRL_IN of the RXTX_BITSLICE buses must connect to the BITSLICE_CONTROL RX/TX_BIT_CTRL_OUT2 buses.

These buses are made of dedicated routing between the BITSLICE_CONTROL and bit slices and cannot be accessed or used by logic. It is also not possible to connect an ILA or VIO to these buses and viewing the buses in simulation is meaningless because the content and bit names of the buses is not disclosed.

RX_BIT_CTRL_IN[39:0]

 

Input

N/A

Input bus from BITSLICE_CONTROL

RX_BIT_CTRL_OUT[39:0]

 

Output

N/A

Output bus to BITSLICE_CONTROL

TX_BIT_CTRL_IN[39:0]

 

Input

N/A

Input bus from BITSLICE_CONTROL

TX_BIT_CTRL_OUT[39:0]

 

Output

N/A

Output bus to BITSLICE_CONTROL

Notes:

1.I/O RX: Connections between the RX_BITSLICE side of the RXTX_BITSLICE and the I/O buffers
I/O TX: Connections between the TX_BITSLICE side of the RXTX_BITSLICE and the I/O buffers
RX FPGA: Connections from/to the RX_BITSLICE side of the RXTX_BITSLICE and the logic
TX FPGA: Connections from/to the TX_BITSLICE side of the RXTX_BITSLICE and the logic