UltraScale Architecture SelectIO Resources User Guide (UG571)

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1.14 English

The TX_BITSLICE _TRI is in all respects a bit slice like the TX_BITSLICE. As the TX_BITSLICE, it contains an output delay that can continuously be corrected for VT variation by the BITSLICE_CONTROL, high-speed output serializing register and serialization logic for 4:1 data, but it does not have a direct user-accessible parallel data input nor does it have a serial output with access to FPGA pins. The input for this primitive comes through the BITSLICE_CONTROL primitive from the 4-bit TBYTE_IN bus, so this bit slice is buried inside a nibble. A block diagram of TX_BITSLICE_TRI is shown in This Figure.

Figure 2-52:      TX_BITSLICE_TRI Block Diagram

X-Ref Target - Figure 2-52


The TX_BITSLICE_TRI can only be used to 3-state bit slices within a nibble. The following TX_BITSLICE_TRI Function section shows how the TX_BITSLICE_TRI is connected between the BITSLICE_CONTROL and TX_BITSLICEs of a nibble.

The four bits from the BITSLICE_CONTROL are serialized and possibly delayed and fed to and through the TX_BITSLICE to the 3-state of an output buffer in the IOB. This mechanism provides the ability to 3-state single bits in a serial output stream. The waveform in This Figure shows the relationship of the TBYTE_IN input of the BITSLICE_CONTROL to the TX_BITSLICE.O output and IOB 3-state buffer.

Figure 2-53:      TX_BITSLICE_TRI Primitive

X-Ref Target - Figure 2-53