TX_BITSLICE_TRI Attributes

UltraScale Architecture SelectIO Resources User Guide (UG571)

Document ID
UG571
Release Date
2022-08-31
Revision
1.14 English
Table 2-29:      TX_BITSLICE_TRI Attributes

Attributes

Values

Default

Type

Description

DATA_WIDTH

4, 8

8

Decimal

Attribute defining the input width of the parallel-to-serial converter.

This specifies the width the data needs to have to be serialized by the parallel-to-serial converter. This value must match RXTX_BITSLICE/TX_BITSLICE DATA_WIDTH.

DELAY_FORMAT

TIME(1), COUNT

TIME

String

DELAY_FORMAT can be either TIME or COUNT.

When set to TIME, the delay after BISC completes (DLY_RDY goes High) equals the delay given in DELAY_VALUE (specified in ps).

BISC uses the REFCLK_FREQUENCY attribute in conjunction with the incoming master clock to determine the current tap size and therefore how many taps are required to achieve the requested TIME value (DELAY_VALUE). This calibration accounts for the process variation in the device. When EN_VTC is High, the delay is calibrated to provide the requested TIME across voltage and temperature.

When DELAY_FORMAT is set to COUNT, the value given in DELAY_VALUE is the number of taps required. EN_VTC must be tied Low when using COUNT.

DELAY_TYPE

FIXED, VAR_LOAD, VARIABLE

FIXED

String

Delay mode of the input delay line.

DELAY_VALUE

0–1250 (TIME UltraScale)

0–1100 (TIME UltraScale+)

0–511 (COUNT)

0

Decimal

TIME mode: Desired value in ps.

UltraScale devices support delays up to 1.25 ns.

UltraScale+ devices support up to 1.1 ns.

COUNT mode: Desired value in taps.

UPDATE_MODE

ASYNC

MANUAL

SYNC

ASYNC

String

ASYNC: Updates to the delay value are independent of the data being received. This mode is the preferred operation mode because it covers the function of both other modes.

SYNC: Updates require DATAIN transitions to synchronously update the delay with the DATAIN edges. This mode is suitable for clocks or data that are always available and switches on a periodic basis.

MANUAL: It takes two assertions of LOAD for the new value to take effect. The first LOAD loads the value defined by CNTVALUEIN and the second LOAD must be asserted with an assertion of the CE for the new value to take effect. This is beneficial because you can update the delay when the data becomes idle.

INIT

1’b1, 1’b0

1’b1

Binary

Defines the initial value of the O port which is the serialized data output of the TX_BITSLICE_TRI.

OUTPUT_PHASE_90

TRUE or FALSE

FALSE

String

The output phase can be chosen to be either 0 or 90 degrees.

DELAY_VALUE must be set to 0 when OUTPUT_PHASE_90 =TRUE.

REFCLK_FREQUENCY

200.00–2400.00 (UltraScale)

300.00–2666.67 (UltraScale+)

300.0

1 significant digit float

Specification of reference clock frequency in MHz.

The reference clock is the master_clock (PLL_CLK) connected to the BITSLICE_CONTROL. This attribute is used in the BISC to calibrate any TIME mode delays.

See Clocking in Native Mode and Built-in Self-Calibration in the BITSLICE_CONTROL section.

The tap size is not determined by the REFCLK_FREQUENCY.

A tap delay range is specified in the UltraScale device data sheets as TIDELAY_RESOLUTION [Ref 2]. The REFCLK_FREQUENCY attribute is used by the BISC algorithm to calculate the number of taps required for the requested DELAY_VALUE.

IS_CLK_INVERTED

1’b0,1’b1

1’b0

Binary

Specifies whether the CLK pin is active-High or active-Low.

Similar to the IS_RST_INVERTED attribute but on the CLK path.

When IS_CLK_INVERTED = 1, the inverter is used.

When IS_CLK_INVERTED = 0, the inverter is not used.

IS_RST_DLY_INVERTED

1’b0,1’b1

1’b0

Binary

Specifies whether the reset RST_DLY pin is active-High or active-Low.

Similar to the IS_RST_INVERTED attribute but on the RST_DLY path.

When IS_RST_DLY_INVERTED = 1, the inverter is used.

When IS_RST_DLY_INVERTED = 0, the inverter is not used.

IS_RST_INVERTED

1’b0,1’b1

1’b0

Binary

Specifies whether the reset RST pin is active-High or active-Low.

There is a selectable local inverter on the reset path that can be used to change the polarity of the reset input.

When IS_RST_INVERTED = 1, the inverter is used.

When IS_RST_INVERTED = 0, the inverter is not used.

NATIVE_ODELAY_BYPASS

TRUE or FALSE

FALSE

String

UltraScale+ FPGAs only: Reserved for memory interface generator (MIG). When TRUE, bypass the ODELAY.

SIM_DEVICE

Possible Values: ULTRASCALE, ULTRASCALE_PLUS, ULTRASCALE_PLUS_ES1, ULTRASCALE_PLUS_ES2

ULTRASCALE

String

Sets the device version (ULTRASCALE, ULTRASCALE_PLUS, ULTRASCALE_PLUS_ES1, ULTRASCALE_PLUS_ES2)

Notes:

1.When in TIME mode, calibration affects the availability of bit slices within the nibble. See Bank Overview for more information.