UltraScale Architecture SelectIO Resources User Guide (UG571)

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1.14 English

As mentioned, a TX_BITSLICE_TRI is a TX_BITSLICE but without user data input and serial output. As such, follow the explanation of the RXTX_BITSLICE Transmitter Function to understand the function of this TX_BITSLICE_TRI.

3-state is mostly used for bidirectional data and/or clock/strobe applications. The TX_BITSLICE_TRI is only used when the RXTX_BITSLICE/TX_BITSLICE attribute TBYTE_CTL is set to TBYTE_IN. In that case, the BITSLICE_CONTROL, TX_BITSLICE_TRI, and one or more TX_BITSLICEs work together to 3-state dedicated bits in a set of serial data output streams. This Figure shows how the primitives are interconnected and the waveform in This Figure shows how signals must be applied in order to 3-state bits in a serial data stream.

When the TBYTE_CTL attribute is set to TBYTE_IN, the TBYTE_IN[3:0] inputs of the BITSLICE_CONTROL primitive control the 3-state of all RXTX_BITSLICEs in a nibble. As shown in This Figure, the TBYTE_IN[3:0] inputs control all nibble output 3-state functions (through the TX_BITSLICE_TRI). By using TBYTEIN[3:0] inputs, it is possible to 3-state a single bit in a serial stream.

When the TBYTE_CTL attribute is set to T, TX_BITSLICE_TRI is not needed and the TBYTE_IN[3:0] pins can be deasserted Low (This Figure). When the TBYTE_CTL attribute is set to T, the 3-state function for that RXTX_BITSLICE is controlled from interconnect logic. Controlling the 3-state of a RXTX_BITSLICE from interconnect logic means that it operates as a block, word, or frame 3-state. As shown in This Figure, it is possible to mix TX_BITSLICEs in a nibble with TBYTE_CTL set to TBYTE_IN and T. When a nibble has a mix of TBYTE_IN and T, alignment of serialized data across the bit slices is not guaranteed.

This Figure shows the required connections when connecting 3-state control using the TX_BITSLICE_TRI and T_BYTE_IN[3:0] of TX_BITSLICE.

Figure 2-54:      Connections for a 3-State Path when Using the TBYTE Port

X-Ref Target - Figure 2-54



Figure 2-55:      Connections for a 3-State Path when Using TBYTE (DATA_WIDTH=8)

X-Ref Target - Figure 2-55


Notes on This Figure:

For easier viewing, latency is not shown.

At the start, BITSLICE_CONTROL.TBYTE_IN is 1111 and the output buffer is not 3-stated. The output of the OBUFT is all ones (11111111).

At event 1, the TBYTE_IN at the BITSLICE_CONTROL is 1010 while the data input is all High. This causes part of the serial data stream to 3-state. The serial stream out of the output buffer O port is 11ZZ11ZZ.

At event 2, the parallel data input is all Low, the TBYTE_IN is 1111, and therefore the data stream is not 3-stated.

At event 3, the TBYTE_IN is 1101 while the parallel input is still zero, therefore the 4th and 5th bits of the parallel word are 3-stated. The D input is all logic Low. The output data is 0000ZZ00.

Figure 2-56:      Using the TBYTE_CTL Attribute Settings TBYTE_IN or T

X-Ref Target - Figure 2-56


The latency for the TX_BITSLICE_TRI is shown in This Figure and This Figure.

Figure 2-57:      3-State Latency, DATA_WIDTH = 8

X-Ref Target - Figure 2-57

Figure 2-58:      3-State Latency, DATA_WIDTH = 4

X-Ref Target - Figure 2-58