TX_BITSLICE_TRI Ports

UltraScale Architecture SelectIO Resources User Guide (UG571)

Document ID
UG571
Release Date
2022-08-31
Revision
1.14 English

Table: TX_BITSLICE_TRI Port Descriptions lists the TX_BITSLICE_TRI ports.

Table 2-28:      TX_BITSLICE_TRI Port Descriptions

Port

I/O

Description

RST

Input

Resets the 3-state serialization logic, asynchronous assertion and synchronous deassertion and is active-High. Q resets to zero while RST is asserted. For deterministic bring-up, follow the steps in Native Mode Bring-up and Reset.

CE

Input

Clock enable for the 3-state delay line register clock.

CLK

Input

Clock input. All control inputs to the DELAY element within the TX_BITSLICE_TRI (LOAD, CE, and INC) are synchronous to this clock input. A clock must be connected to this port when DELAY is configured in VARIABLE or VAR_LOAD. This signal can be locally inverted, and must be supplied by a global or regional clock buffer.

The clock signal connected to this pin must be the same clock signal as the one connected to the RX_CLK and/or CLK of a RXTX_BITSLICE/RX_BITSLICE.

INC

Input

The increment/decrement is controlled by the enable signal (CE). This interface is only available when the delay line is in VARIABLE or VAR_LOAD mode.

As long as CE remains High, the delay line is incremented or decremented by one tap every clock (CLK) cycle. The state of INC determines whether delay line is incremented or decremented: INC = 1 increments; INC = 0 decrements, synchronously to the clock (CLK).

If CE is Low, the delay through the delay line does not change (regardless of the state of INC). When CE goes High, the increment/decrement operation begins on the next positive clock edge. When CE goes Low, the increment/decrement operation ceases on the next positive clock edge.

The programmable delay taps in the delay line primitive wrap around. When the last tap delay is reached (CNTVALUEOUT = 511), a subsequent increment function returns to tap 0. The same applies to the decrement function: decrementing from zero moves to tap 511.

LOAD

Input

When in VAR_LOAD mode, this input loads the value set by the CNTVALUEIN attribute into the delay line. The value present at CNTVALUEIN[8:0] is the new tap value. The LOAD signal is an active-High signal and is synchronous to the input clock signal (CLK). Wait at least one clock cycle after applying a new value on the CNTVALUEIN bus before applying the LOAD signal. The CE must be held Low during LOAD operation.

CNTVALUEIN[8:0]

Input

The CNTVALUEIN bus is used to dynamically change the loadable tap value. The 9-bit value at the CNTVALUEIN is the number of taps required. The new value is to be presented one CLK cycle before LOAD is pulsed High. New CNTVALUEIN values should only be applied when EN_VTC is Low.

CNTVALUEOUT[8:0]

Output

The CNTVALUEOUT pins are used for reporting the current tap value. CNTVALUEOUT should only be sampled when EN_VTC is Low.

RST_DLY

Input

Resets the delay line taps setting to the value provided by the DELAY_VALUE attribute.

Reset port for the delay line in the TX_BITSLICE_TRI.

EN_VTC

Input

Enable Voltage Temperature calibration.

High: Allows BITSLICE_CONTROL to keep delay constant over VT. BITSLICE_CONTROL.EN_VTC must be held High for VT compensation to be enabled.

Low: VT compensation is disabled.

When TIME mode is used, the EN_VTC signal must be pulled High during initial BISC.

When COUNT mode is used, the EN_VTC signal must be pulled Low.

BIT_CTRL_IN[39:0]

Input

Input bus from BITSLICE_CONTROL. Dedicated pins that must connect directly between the BITSLICE_CONTROL and TX_BITSLICE_TRI and to nothing else in the design.

BIT_CTRL_OUT[39:0]

Output

Output bus to BITSLICE_CONTROL. Dedicated pins that must connect directly between the BITSLICE_CONTROL and TX_BITSLICE_TRI and to nothing else in the design.

TRI_OUT

Output

3-state output (TRI_OUT) outputs to the TBYTE_IN pins of the bit slices.