Transmit Clocking

UltraScale Architecture SelectIO Resources User Guide (UG571)

Document ID
UG571
Release Date
2023-08-31
Revision
1.15 English

When transmitting data, the master input clock of the BITSLICE_CONTROL is used to shift data out of the transmitter ( This Figure ). The frequency of this clock determines the serial bit rate of the data. Data must be presented at the RXTX_BITSLICE transmitter inputs at a clock running at the master clock divided by the DIV_MODE and/or DATA_WIDTH attribute setting.

Figure 2-67: Data Transmission

X-Ref Target - Figure 2-67

X16051-data-transmission.jpg

Notes on This Figure :

When a serial data stream of 1 Gb/s is required, then the PLL in the same I/O bank as the TX_BITSLICEs must deliver a 1 GHz clock at the PLL_CLK input of the BITSLICE_CONTROL.

When the TX_BITSLICEs are operated in 8-bit mode (DATA_WIDTH = 8), the data must be presented at the D inputs of the TX_BITSLICE with a 125 MHz clock (1 GHz/DIV_MODE = 4).

TIP: Using the OUTPUT_PHASE_90 attribute allows the serial output of a transmitter bit slice to be phase-shifted by 90 degrees. This function is normally used to generate center-aligned interface clocks. When using OUTPUT_PHASE_90, DELAY_VALUE should not be used.