The HR I/O and HP I/O banks have an optional uncalibrated input on-chip split-termination feature for HSTL and SSTL standards and a single-termination feature for POD and HSUL standards that are similar to the DCI feature. This option creates a Thevenin equivalent circuit using two internal resistors of twice the target resistance value (2R where R = Z0) for HSTL and SSTL standards. One resistor terminates to VCCO and the other to GND, providing a Thevenin equivalent termination circuit of half the resistor value to the mid-point VCCO/2 for HSTL and SSTL standards. A single resistor terminates to VCCO for POD and HSUL standards.
The termination is present constantly on inputs, and on bidirectional pins whenever the output buffer is 3-stated except when DCITERMDISABLE (in HP I/O banks) or INTERMDISABLE (in HR I/O banks) are asserted. However, an important difference between this uncalibrated option and DCI is that instead of calibrating to an external reference resistor on the VRP pin when using DCI, the uncalibrated input termination feature invokes internal resistors determined by the ODT attribute that have no calibration routine to compensate for temperature, process, or voltage variations.
•Possible ODT values for split-termination standards (HSTL and SSTL) are RTT_40, RTT_48, RTT_60, or RTT_NONE.
•Possible values for ODT for single-termination POD standards are RTT_40, RTT_48, RTT_60, or RTT_NONE.
•Possible values for ODT for single-termination HSUL standards are RTT_120, RTT_240, or RTT_NONE.
The main difference in how DCI or uncalibrated termination is invoked in a design is whether or not a DCI I/O standard is chosen. In both DCI and uncalibrated I/O standards, the values of the termination resistors are determined by the ODT attribute.
Table: I/O Standards that Support Uncalibrated Termination shows a list of I/O standards that support the uncalibrated termination in both the HR and HP I/O banks.