VAR_LOAD Mode

UltraScale Architecture SelectIO Resources User Guide (UG571)

Document ID
UG571
Release Date
2022-08-31
Revision
1.14 English

 

Figure 2-44:      VAR_LOAD Mode, UPDATE_MODE = ASYNC

X-Ref Target - Figure 2-44

X17479-var_load-mode-update_mode-is-async-jWzNxxD4.jpg

When the DELAY_TYPE attribute is set to VAR_LOAD, the delay line can be changed using the CE and INC inputs or the CNTVALUEIN, CNTVALUEOUT, and LOAD pins can be used to parallel load the delay line tap selection. Using these inputs, the delay line can be changed from 1 to 8 taps at a time.

The VAR_LOAD method is suitable for both COUNT and TIME mode usage of the delay line.

In both modes, the tap amount can be read from the CNTVALUEOUT bus and changed through the CNTVALUEIN bus or CE and INC ports if necessary.

Note:   The procedure to calculate the value to update the delay line is different for input and output delay lines. The procedure to calculate the value to update the delay line is different for TIME and COUNT mode.

If DELAY_TYPE is VAR_LOAD and DELAY_FORMAT is TIME/COUNT, the procedure to update the delay line follows (This Figure):

1.After BITSLICE_CONTROL.DLY_RDY goes High, BITSLICE_CONTROL.EN_VTC must be pulled High during the reset sequence.

2.When BITSLICE_CONTROL.VTC_RDY goes High, BISC has completed. Make RXTX_BITSLICE.EN_VTC Low to modify the delay line.

3.Wait at least 10 clock cycles.

4.Read CNTVALUEOUT[8:0] and load the value into a register.

5.Check if updating the delay line is necessary.

6.Calculate the new delay value to be written in the delay line.

a.Increment or decrement the current tap position (Org_Val) by 8 taps for glitchless transition. Jumps higher than 8 taps might result in the delay line jump causing data to glitch. For outputs, the glitch can corrupt the serialization.

Note:   For the last pass, fewer than 8 taps might be needed.

b.Put the new delay line value on the CNTVALUEIN[8:0] bus.

c.Wait for one clock cycle and pulse LOAD High for a clock cycle.

d.Check if the new delay line value (New_Val) is reached.

-If not, continue from step a.

-If so, continue with step 7.

or

a.Calculate the difference (Dif_Val) between New_Val and Org_Val and the direction to step.

b.Make the INC input High or Low to increment or decrement the delay line.

c.Toggle the CE pin to execute the increment or decrement.

d.Decrement the Dif_Val and check if it is zero.

-If not, continue from step a.

-If so, continue to step 7.

7.Wait for at least 10 clock cycles.

8.Pull RXTX_BITSLICE.EN_VTC back High.

9.Go back to step 2 for a new delay line update.