ZHOLD

UltraScale Architecture SelectIO Resources User Guide (UG571)

Document ID
UG571
Release Date
2022-08-31
Revision
1.14 English

The ILOGIC block supports an optional static uncompensated zero hold (ZHOLD) delay line on inputs to compensate for clock insertion delay. The ZHOLD feature is optimized to compensate for the clock insertion delays when the clocking path is directly sourced from a BUFG/BUFGCE, which is sourced in the same bank or on an adjacent bank. ZHOLD is enabled by default unless the clock source is a MMCM/PLL or unless the IOBDELAY attribute is set in the XDC.

 

IMPORTANT:   ZHOLD might not be appropriate for all applications, so consult the timing report to verify the impact to a specific clocking scheme.