UltraScale Architecture Clocking Resources User Guide (UG572)

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1.10.2 English

BUFGCE_1 is a clock buffer with one clock input, one clock output, and a clock enable line. This primitive is based on BUFGCTRL with some pins connected to logic High or Low. This Figure illustrates the relationship of BUFGCE_1 and BUFGCTRL. The LOC constraint is available for manually placing the BUFGCE_1 location. See the Vivado Design Suite User Guide: Using Constraints (UG903) [Ref 4] for more information.

Figure 2-7: BUFGCE_1 as BUFGCTRL

X-Ref Target - Figure 2-7


The switching condition for BUFGCE_1 is similar to BUFGCTRL with INIT_OUT set to 1. If the CE input is Low prior to the incoming falling clock edge, the following clock pulse does not pass through the clock buffer, and the output stays High. Any level change of CE during the incoming clock Low pulse has no effect until the clock transitions High. The output stays High when the clock is disabled. However, when the clock is being disabled, it completes the clock Low pulse.

IMPORTANT: Because the clock enable line uses the CE pin of the BUFGCTRL, the select signal must meet the setup time requirement. Violating this setup time can result in a glitch.

This Figure illustrates the timing diagram for BUFGCE_1.

Figure 2-8: BUFGCE_1 Timing Diagram

X-Ref Target - Figure 2-8