CDDCREQ – Request a Clock Output Divide Change

UltraScale Architecture Clocking Resources User Guide (UG572)

Document ID
UG572
Release Date
2023-02-01
Revision
1.10.2 English

This is a request signal for dynamically changing the output clock divide value and therefore the frequency. When asserted High, a request is sent to all affected counters and must stay asserted until the last change via the DRP has been completed.