This is a request signal for dynamically changing the output clock divide value and therefore the frequency. When asserted High, a request is sent to all affected counters and must stay asserted until the last change via the DRP has been completed.
This is a request signal for dynamically changing the output clock divide value and therefore the frequency. When asserted High, a request is sent to all affected counters and must stay asserted until the last change via the DRP has been completed.