CLKOUT[0:6] – Output Clocks

UltraScale Architecture Clocking Resources User Guide (UG572)

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1.10.2 English

These user-configurable clock outputs (CLKOUT0 through CLKOUT6) can be divided versions of the VCO phase outputs (user controllable) from 1 (bypassed) to 128. The input clock and output clocks can be phase aligned.

RECOMMENDED: CLKOUT0 is first used to place the root clock point. In ZHOLD mode, it is used to set the compensation. Therefore, Xilinx recommends using CLKOUT0 as the main clock.

For possible configurations, see MMCM Use Models . In the MMCM, CLKOUT0 and CLKFBOUT can be used in fractional divide mode. All CLKOUT outputs can be used in non-fractional mode to provide a static or dynamic phase shift. In fractional mode, only fixed phase shift is allowed. See Static Phase Shift Mode (MMCM and PLL) for more information.