CLKOUTPHYEN – PHY Clock Enable

UltraScale Architecture Clocking Resources User Guide (UG572)

Document ID
UG572
Release Date
2023-02-01
Revision
1.10.2 English

CLKOUTPHYEN enables the CLKOUTPHY clock outputs. The PLL employs enable logic to synchronize the asynchronous CLKOUTPHYEN signal from your design and controls when the CLKOUTPHY clocks are released. After the CLKOUTPHY clock is released, the rising edge is aligned to the rising edge of the input clock CLKIN. Glitch-free enabling and disabling of the CLKOUTPHY output clock is assured for all configurations.

However, phase alignment between multiple PLL CLKOUTPHY clocks is only assured when both the CLKFBOUT_MULT and CLKOUT[0:1]_DIVIDE values are set to 1, 2, 4, or 8. Rising edges do not align for CLKFBOUT = 3, 5, 6, 7, 9,...