Clock Buffers

UltraScale Architecture Clocking Resources User Guide (UG572)

Document ID
Release Date
1.10.2 English

The PHY global clocking contains several sets of BUFGCTRLs, BUFGCEs, and BUFGCE_DIVs. Each set can be driven by four GC pins from the adjacent bank, MMCMs, PLLs in the same PHY , and interconnect. The clock buffers then drive the routing and distribution resources across the entire device. Each PHY contains 24 BUFGCEs, 8 BUFGCTRLs, and 4 BUFGCE_DIVs but only 24 of them can be used at the same time.

IMPORTANT: It is recommended to only allow the Vivado ® Placer to assign all global clock buffers to specific locations. Each CR contains 24 BUFGCEs, 8 BUFGCTRLs and 4 BUFGCE_DIVs. These clock buffers share the 24 routing tracks and therefore collisions may occur resulting in unroutable designs. If the design requires a number of global clock buffers to be in a certain CR then it is recommended to attach the CLOCK_REGION property to these buffers instead of a specific LOCATION property.

In the clocking architecture, BUFGCTRL multiplexers and all derivatives can be cascaded to adjacent clock buffers, effectively creating a ring of eight BUFGMUXes (BUFGCTRL multiplexers). This Figure shows a simplified diagram of cascading BUFGCTRLs.

Figure 2-4: Cascading BUFGCTRLs

X-Ref Target - Figure 2-4


The following subsections detail the various configurations, primitives, and use models of the clock buffers.