Clock Network Deskew

UltraScale Architecture Clocking Resources User Guide (UG572)

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1.10.2 English

One of the predominant uses of the MMCM is for clock network deskew. This Figure shows the MMCM in this mode. The clock output from one of the CLKOUT counters is used to drive logic within the device and/or the I/Os. The feedback counter is used to control the exact phase relationship between the input clock and the output clock (if, for example a 90° phase shift is required). The associated clock waveforms are shown to the right for the case where the input clock and output clock need to be phase aligned. The configuration in This Figure is the most flexible, but it does require two global clock networks.

Figure 3-9: Global Clock Network Deskew Using Two BUFGs

X-Ref Target - Figure 3-9


There are certain restrictions on implementing the feedback. The CLKFBOUT output can be used to provide the feedback clock signal. When an MMCM is driving both BUFGs and BUFGCTRL, only one of the clock buffers that is also used in the feedback path is deskewed. The fundamental restriction is that both input frequencies to the PFD must be identical. Therefore, this relationship must be met:

Equation 3-11 ug572_c3_Clock_Management00055.jpg

As an example, if ƒ IN is 166 MHz, D = 1, M = 6, and O = 2, then VCO is 996 MHz and the clock output frequency is 498 MHz. Because the M value in the feedback path is 6, both input frequencies at the PFD are 166 MHz.

Another more complex scenario has an input frequency of 66.66 MHz and D = 2, M = 30, and O = 4. The VCO frequency in this case is 1000 MHz and the CLKOUT output frequency is 250 MHz. Therefore, the feedback frequency at the PFD is 1000/30 or 33.33 MHz, matching the 66.66 MHz/2 input clock frequency at the PFD.