Clocking in a design is not just applying clock buffers, instantiating MMCM and/or PLL, and applying one or a couple of constraints in a XDC file. Clocking and the setup of a clocking network needs attention. To create a design, that is implemented (synthesize, place, and route) using all of Vivado Design Suite features, and when downloaded makes the FPGA function at optimal conditions, follow the guidelines provided in the chapters Clocking Guidelines and Clock Domain Crossing of the UltraFast Design Methodology Guide for the Vivado Design Suite (UG949) [Ref 1] .
The UltraFast Design Methodology Guide for the Vivado Design Suite (UG949) [Ref 1] offers a set of best practices intended to help streamline the design process for new devices. The size and complexity of these designs require specific steps and design tasks to ensure success at each stage of the design. Following these steps and adhering to the best practices will help you achieve your desired design goals as quickly and efficiently as possible. Two other documents that can be useful for designing are:
• UltraFast Design Methodology Quick Reference Guide (UG1231) [Ref 9]
• UltraFast Design Methodology Checklist (XTP301) [Ref 10]