DRP Register Set

UltraScale Architecture Clocking Resources User Guide (UG572)

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1.10.2 English

The user accessible DRP register set is described in this section. The DRP register map spans from address 0x00 to address 0x7F (7-bit address bus). The figure below shows the layout of the register map of user accessible registers. Be aware that values of different counters overlap register boundaries.

Figure 3-23: MMCM DRP Register Set

X-Ref Target - Figure 3-23


IMPORTANT: When operating a DRP port, it is recommended that the existing contents of the register that is going to be changed are first read. Write back the register contents where only the required bits are modified. Modify only the colored bits and always maintain the state of the gray bits.