Dynamic Reconfiguration Port

UltraScale Architecture Clocking Resources User Guide (UG572)

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1.10.2 English

In most circumstances, the MMCM and/or PLL used in a design are configured using static calculated values to setup the used outputs. A wizard can be used to calculate all the values and generate an instantiable wrapper containing a configured MMCM or PLL. The MMCM and/or PLL primitive can also be instantiated as primitives and the values to make the primitive function correctly can be calculated using the equations provided in the MMCM Programming section.

The DRP port provides the ability to use a MMCM and/or PLL as a dynamic element in a design. The DRP port setup is that of a common microcontroller peripheral and gives the user access to a set of registers in the MMCM or PLL. These registers allow the user to fully control the MMCM or PLL. Inputs pins and the values to define output clocks are turned into register bits making it possible to use the primitives as active elements in a design.

Using the DRP port means reading and writing of registers of a peripheral. When using the Clocking Wizard the DRP port can be enabled through an AXI-Lite controller to a hard or soft microcontroller in the FPGA. Nevertheless, it might be necessary by design and other requirements to use the DRP port in a bare metal configuration (also selectable in the Clocking Wizard). The DRP port can then be used as such through a state machine based design. To help with this the provided description of the functioning of the DRP port can be used.

For additional DRP usage information, see MMCM and PLL Dynamic Reconfiguration (XAPP888) [Ref 6] and the associated reference.

The DRP port connections are shown in the following figure.

Figure 3-19: DRP Port Connections

X-Ref Target - Figure 3-19

Table 3-13: DRP Port Signals








The DCLK signal is the reference clock for the dynamic reconfiguration port. This clock is normally about 100 MHz to 200 MHz. The newer the technology of the FPGA family used, the faster this clock can be.




The dynamic reconfiguration enable (DEN) provides the enable control signal to access the dynamic reconfiguration feature. When the dynamic reconfiguration feature is not used, DEN must be tied Low.




The dynamic reconfiguration write enable (DWE) input pin provides the write enable control signal to write the data on the DI port into the register selected by the DADDR address. When not used, DWE must be tied Low.


n (1)


The dynamic reconfiguration address (DADDR) input bus provides a reconfiguration address to access a specific register in the primitive for dynamic reconfiguration. When not used, all bits must be assigned zeros.




The dynamic reconfiguration data input (DI) bus provides reconfiguration data that is written into a specified address (DADDR) of the register set. When not used, all bits must be set to zero.




The dynamic reconfiguration output bus provides data output of the register selected by the DADDR bus. This port can be used to control DRP register contents.




The dynamic reconfiguration ready output (DRDY) provides the response to the DEN signal for the PLLs dynamic reconfiguration feature. This signal is pulsed high when a write or read operation is successful.


1. The width of the DADDR bus depends on the primitive that the DRP port is a part of. For a MMCM, the address bus is 7-bit wide and for a PLL the DRP address bus is 7-bit wide (DADDR(6:0)). The DADDR port of an ADC/DAC in a RFSoC device is 12-bit wide while the DADDR port of a GTP is 10-bit wide.