Frequency Synthesis Using Fractional Divide in the MMCM

UltraScale Architecture Clocking Resources User Guide (UG572)

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1.10.2 English

Devices support fractional (non-integer) divides in the CLKOUT0 output path. The resolution of the fractional divide is 1/8 or 0.125, effectively increasing the number of synthesizeable frequencies by a factor of eight. For example, if the CLKIN frequency is 100 MHz and the M divide value is set to 8, the VCO frequency is 800 MHz. CLKOUT0 can be used to further fractionally divide the 800 MHz VCO frequency (e.g., CLKOUT0_DIVIDE = 2.5, resulting in a 320 MHz output frequency).

When using the fractional divider, the duty cycle is not programmable for outputs used in the fractional mode.