Key Differences from 7 Series FPGAs

UltraScale Architecture Clocking Resources User Guide (UG572)

Document ID
Release Date
1.10.2 English

BUFMRs, BUFRs, and BUFIOs, and the associated routing resources have been removed from this architecture and are replaced by new clock buffers, clock routing, and a completely new I/O clocking architecture.

The BUFGCTRL and its derivatives are still available. Two new global clock buffer resources BUFGCE and BUFGCE_DIV have been introduced in the new architecture. At the local clocking level, a new BUFCE_LEAF clock buffer provides local, vertical clocking with additional features.

A BUFG_GT buffer for clock division of GT clocks has been added.

A new and improved clock routing architecture is available. There are now two types of global routing tracks called routing and distribution. Both types of routing provide a segmentable clock network at the CR level. Both types can be driven by the global clock buffers. The distribution tracks can be driven by routing tracks or directly by clock buffer resources. The distribution tracks provide connectivity to all clocking points in UltraScale devices .

The CMTs now have two PLLs instead of one.

MMCMs are similar to the MMCM in the 7 series devices. PLLs have new features related to I/O PHY clocking. However, other clocking related functionality and connectivity has been reduced as compared to the 7 series FPGAs. For example, the PLLs do not support phase compensation or external feedback, have fewer outputs, share a voltage-controlled oscillator (VCO) with the PHY clocking, and have other features removed as compared to the 7 series devices. For this reason, most customers should use the MMCM for general clocking. However, leftover PLLs are also available for use.

The MMCM output clock frequencies can be dynamically changed without resetting the MMCM.

The definition of clock region has changed. A clock region no longer spans half a device width in the horizontal direction. UltraScale architecture clock regions have a rectangular shape with a fixed width and height and are organized in tiles. Horizontal and vertical clock tracks are segmented at the clock region boundaries.

The clock capable pins (CC) have been replaced by global clock pins (GC). In addition, the UltraScale+ architecture has high-density (HD) I/O banks. These banks contain four global clock pins called HDGC which can connect to the BUFGCEs.