MMCM Clock Divide Dynamic Change

UltraScale Architecture Clocking Resources User Guide (UG572)

Document ID
Release Date
1.10.2 English

The Clock Divide Dynamic Change (CDDC) feature supports the dynamic change of the clock output dividers (CLKOUT[6:0]_DIVIDE) in conjunction with the DRP interface without the need for resetting the MMCM. Effectively, one or more of the MMCM output clock frequencies can be changed while leaving other output clocks untouched and running continuously. Two pins (CDDCREQ and CDDCDONE) control the handshaking. The application requests a change of output counter values (the CLKOUT_DIVIDE value) by asserting the CDDCREQ signal. New values are written through the standard DRP interface one port at a time and governed by standard DRP protocol (DEN, DWE, and DRDY). The DRP address of the CLKOUT[6:0] counter written to determines which output clocks are affected. After a CLKOUTx counter is written to, the associated clock output stops toggling. This can be followed by more changes (DRP writes) to other CLKOUT counters in an identical fashion. When all DRP writes have been completed (after the last DRDY), the CDDCREQ input must be deasserted, after which the affected output counter(s) are synchronously restarted. The MMCM acknowledges that the changes have taken place and the new output clocks (frequencies) are available for use by asserting CDDCDONE.

CLKOUT ports not affected by the CDDC change continue to function uninterrupted during this operation and maintain their phase relationship to each other ( This Figure ). However, the output clocks (ports) that were changed via the CDDC procedure are not phase aligned (synchronized) to the other output clocks not affected by CDDCREQ. Clocks affected by CDDCREQ should not be used after the signal has been asserted because the output might glitch and the clocks stop toggling. This feature is not available in fractional mode.

Figure 3-5: CDDC Timing Diagram

X-Ref Target - Figure 3-5